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Product details

Parameters

Arm CPU 1 Arm Cortex-A8 Arm MHz (Max.) 1000 DSP 0 Operating systems Linux Video acceleration 1 HDVICP2 Video port (configurable) 2 Output, 2 Input, 1 SD DAC, 3 HD DACs, 1 HDMI TX On-chip L2 cache/RAM 256 KB (ARM) DRAM 32, bit, DDR2, DDR3, DDR3L PCI/PCIe PCIe, x1, with, PHY Ethernet MAC 10/100/1000 Switch USB 2 USB2.0 w/Phy SPI 4 I2C 4 UART (SCI) 3 Operating temperature range (C) -40 to 95, 0 to 95 Display Two 165-MHz HD Video Display Outputs, HDMI TX Rating Catalog Approx. price (US$) 22.84 | 1ku open-in-new Find other Audio & media processors

Features

  • High-Performance DaVinci Digital Media Processors
    • Up to 1000-MHz ARM® Cortex™-A8 RISC Processor
    • Up to 2000 ARM Cortex-A8 MIPS
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache with ECC
    • 64KB of RAM, 48KB of Boot ROM
  • 256KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
      • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect (FD) Engine
    • Hardware Face Detection for up to 35 Faces Per Frame
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
    • Fourth-Generation Motion-Compensated Noise Filter (DM388 Only)
  • Media Controller
    • Controls the HDVPSS, HDVICP2, and ISS
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Inputs
      • One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
      • One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
    • Component HD Analog Output
    • Composite Analog Output
    • Digital HDMI 1.3 Transmitter with Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
    • Three Graphics Layers and Compositors
  • 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
    • Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
    • Up to Two x 16 Devices, 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Total Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels
    • 8 QDMA Channels
  • Ethernet Switch with Dual 10-, 100-, or
    1000-Mbps External Interfaces (EMAC Software)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts
    • Supports End Points 0-15
  • One PCI Express 2.0 Port with Integrated PHY
    • Supported on
      • All DM385 Devices
      • DM388 Devices with PCIe Enabled
    • Single Port with 1 Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Three Configurable UART/IrDA/CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
    • Each with Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
    • Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus™) Ports
  • Two Multichannel Audio Serial Ports (McASP)
    • Six Serializer Transmit and Receive Ports
    • Two Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Four Audio Tracking Logic (ATL) Modules
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 125 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex™ Technology (Level 2b)
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Multiple Operating Points per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
  • 45-nm CMOS Technology
  • 1.8- and 3.3-V Dual Voltage Buffers for General I/O

All trademarks are the property of their respective owners.

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Description

DM385 and DM388 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD, HD, and 4K x 2K resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DM388 is uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; a Spin Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.

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Support through a third party

This product does not have ongoing direct design support from TI. For support while working through your design, you may contact one of the following third parties: D3 Engineering, elnfochips, Ittiam Systems, Path Partner Technology, or Z3 Technologies.

Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The DM38x Camera Starter Kit (CSK) enables developers to begin designing wireless or wired connected digital video applications, such as security cameras, car DVRs, endoscopes, action-wearable cameras, drones, video doorbells, baby monitors, and other connected video products.

The DM38x (...)

Features
  • TMDSCSK388: 60-mm x 44-mm DM388 processor board
  • TMDSCSKCC: 90-mm x 90-mm I/O common carrier board
  • Integrated WiLink 8 single-band combo 2 x 2 MIMO WiFi, Bluetooth, and Bluetooth Smart (low energy) module
  • IPNC SDK with Linux 4.4 LTS kernel preloaded on included SD card enables fast application (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The DM38x Digital Video Evaluation Module (DVEVM) enables developers to start immediate evaluation of the DM38x Digital Media Processors and begin building digital video applications such as IP security cameras, action cameras, drones, video doorbells, car digital video recorders and other digital (...)

Features
  • DM388 digital media processor-based development board with 2Gb DDR3
  • Video capture and output of NTSC or PAL signals via component I/O
  • HDMI video output
  • CSI2 and parallel camera input
  • PCIe, SATA 2x, ethernet 2x, USB x2, audio, SD-card slot

Software development

DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
$295.00
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$995.00
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$1,495.00
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Reference designs

REFERENCE DESIGNS Download
DM388 IP Camera Reference Design
TMDSIPCAM388X36 Single platform solution provides SVCT/H.264 1080P 60 fps + SVCT/H.264 D1 30 fps + MJPEG 1080P 5 fps, and up to 10 megapixels at reduced frame rate. Supports TI’s 4th Generation Noise Filter and Local tone mapping dual frame merged WDR together with SVCT/H.264 1080P 30 fps.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
IP Net Camera Power Module Reference Solution
SAT0027 The SAT0027 IP Camera power module, is a highly efficient power solution that enables high performance 1080p IP Camera operation at the Class 1 PoE power level. This innovative power module relies on highly efficient switchers like the TPS5432 that are also very cost effective. The result is, TI (...)

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Package Pins Download
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