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The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high-speed point-to-point interface applications.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS90C032B LVDS Quad CMOS Differential Line Receiver datasheet (Rev. C) | Apr 12, 2013 | |
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | Aug 3, 2018 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | May 16, 2018 | ||
| Application note | AN-1110 LVDS Quad Dynamic I CC vs Frequency | May 15, 2004 | ||
| Application note | An Overview of LVDS Technology | Oct 5, 1998 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
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