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The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabytes/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Display application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vsync, DE and CNTL).
The DS90CF384AQ device is enhanced over prior generation FPD-Link receivers, provides a wider data valid time on the receiver output and is offered as an AEC-Q100 grade 3 device.
FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz datasheet (Rev. A) | Apr 17, 2013 | |
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | Jun 29, 2018 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | Aug 8, 2017 | ||
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | May 15, 2004 | ||
| Application note | AN-1056 STN Application Using FPD-Link | May 14, 2004 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | May 14, 2004 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
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