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The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz datasheet (Rev. A) | Feb 19, 2013 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | Nov 9, 2018 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | Jan 13, 2016 | |
| Application note | Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) | Apr 26, 2013 | ||
| Design guide | Channel Link I Design Guide | Mar 29, 2007 | ||
| Application note | Multi-Drop Channel-Link Operation | Oct 4, 2004 | ||
| Application note | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | Oct 5, 1998 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |
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