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DS90CR218A

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+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 85 MHz

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Data sheet

DS90CR218A

ACTIVE
Data sheet Order now

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • 12 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Low Power Consumption
  • ±1V Common-mode Range (Around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.785 Gbps Throughput
  • Up to 223 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-Lead TSSOP Package

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  • 12 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Low Power Consumption
  • ±1V Common-mode Range (Around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.785 Gbps Throughput
  • Up to 223 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-Lead TSSOP Package

All trademarks are the property of their respective owners.

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet DS90CR218A 3.3VRising Edge Data Strobe LVDS 21Bit Chan Link 12MHz to 85MHz datasheet (Rev. D) Apr 22, 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs Nov 9, 2018
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices PDF | HTML Jan 13, 2016
Application note AN-1538 Interfacing Nationals DS90CR218A and LM98714 (Rev. C) Apr 26, 2013
Design guide Channel Link I Design Guide Mar 29, 2007
Application note Multi-Drop Channel-Link Operation Oct 4, 2004
Application note CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications Oct 5, 1998

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Simulation model

DS90CR218A IBIS Model

SNLM058.ZIP (5 KB) - IBIS model
Supported products & hardware
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TSSOP (DGG) 48 Ultra Librarian
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