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Product details

Parameters

Vn at 1 kHz (nV/rtHz) 0.8 Breakdown voltage (V) 40 VDS (V) 40 VGS (V) -40 VGSTH typ (V) -1.2 Rating Catalog Operating temperature range (C) -40 to 125 open-in-new Find other High-performance transistors

Package | Pins | Size

SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 open-in-new Find other High-performance transistors

Features

  • Ultra-low noise:
    • Voltage noise:
      • 0.8 nV/√Hz at 1 kHz, IDS = 5 mA
      • 0.9 nV/√Hz at 1 kHz, IDS = 2 mA
    • Current noise: 1.8 fA/√Hz at 1 kHz
  • Low gate current: 10 pA (max)
  • Low input capacitance: 24 pF at VDS = 5 V

  • High gate-to-drain and gate-to-source breakdown voltage: –40 V

  • High transconductance: 68 mS

  • Packages: Small SC70 and SOT-23 (Preview)

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Description

The JFE150 is a Burr-Brown™ discrete JFET built using Texas Instruments’ modern, high-performance, analog bipolar process. The JFE150 features performance not previously available in older discrete JFET technologies. The JFE150 offers the maximum possible noise-to-power efficiency and flexibility, where the quiescent current can be set by the user and yields excellent noise performance for currents from 50 µA to 20 mA. When biased at 5 mA, the device yields 0.8 nV/√Hz of input-referred noise, giving ultra-low noise performance with extremely high input impedance (> 1 TΩ). The JFE150 also features integrated diodes connected to separate clamp nodes to provide protection without the addition of high leakage, nonlinear external diodes.

The JFE150 can withstand a high drain-to-source voltage of 40-V, as well as gate-to-source and gate-to-drain voltages down to –40 V. The temperature range is specified from –40°C to +125°C. The device is offered in 5-pin SOT-23 and SC-70 packages.

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Technical documentation

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* Data sheet JFE150 Ultra-Low Noise, Low Gate Current, Audio, N-Channel JFET datasheet Jun. 28, 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

The (...)

Features
  • Simplifies prototyping of SMT IC’s
  • Supports 6 common package types
  • Low Cost

Design tools & simulation

SIMULATION MODEL Download
SLPM349.ZIP (131 KB) - PSpice Model
SIMULATION MODEL Download
SLPM350.ZIP (2 KB) - TINA-TI Spice Model
SIMULATION MODEL Download
SLPM351.TSC (70 KB) - TINA-TI Reference Design
SIMULATION MODEL Download
SLPM352.ZIP (15 KB) - TINA-TI Reference Design
SIMULATION MODEL Download
SLPM353.ZIP (140 KB) - PSpice Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
SC70 (DCK) 5 View options

Ordering & quality

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