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Arm CPU 1 Arm9 Arm MHz (Max.) 192 Co-processor(s) DSP CPU 32-bit Hardware accelerators Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and MotionEstimation for Video Compression Operating system Linux, RTOS Rating Catalog open-in-new Find other Arm-based processors

Package | Pins | Size

NFBGA (GVL) 289 144 mm² 12 x 12 NFBGA (ZVL) 289 144 mm² 12.1 x 12.1 open-in-new Find other Arm-based processors

Features

  • Low-Power, High-Performance CMOS Technology
    • 0.13-µm Technology
    • 1.6-V Core Voltage
  • TI925T (MPU) ARM9TDMI™ Core
    • Support 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • Data and Program Memory Management Units (MMUs)
    • Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs
    • 17-Word Write Buffer
  • TMS320C55x™ (C55x™) DSP Core
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers (Two Multiply-Accumulates per Cycle)
    • Two Arithmetic/Logic Units
    • One Internal Program Bus
    • Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses)
    • 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes)
    • 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes)
    • 16K x 16-Bit On-Chip ROM (32K Bytes)
    • Instruction Cache (24K Bytes)
    • Video Hardware Accelerators for DCT, IDCT, Pixel Interpolation, and Motion Estimation for Video Compression
  • 192K Bytes of Shared Internal SRAM
  • Memory Traffic Controller (TC)
    • 16-Bit EMIFS External Memory Interface to Access up to 128M Bytes of Flash, ROM, or ASRAM
    • 16-Bit EMIFF External Memory Interface to Access up to 64M Bytes of SDRAM
  • 9-Channel System DMA Controller
  • DSP Memory Management Unit
  • Endianism Conversion Logic
  • Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC Clocking Control
  • DSP Peripherals
    • Three 32-Bit Timers and Watchdog Timer
    • Level1/Level2 Interrupt Handlers
    • Six-Channel DMA Controller
    • Two Multichannel Buffered Serial Ports
    • Two Multichannel Serial Interfaces
  • TI925T Peripherals
    • Three 32-Bit Timers and Watchdog Timer
    • 32-kHz Timer
    • Level1/Level2 Interrupt Handlers
    • USB (Full/Low Speed) Host Interface With up to 3 Ports
    • USB (Full Speed) Function Interface
    • One Integrated USB Transceiver for Either Host or Function
    • Multichannel Buffered Serial Port
    • Inter-Integrated Circuit (I2C) Master and Slave Interface
    • Microwire™ Serial Interface
    • Multimedia Card (MMC) and Secure Digital (SD) Interface
    • HDQ/1-Wire® Interface
    • Camera Interface for CMOS Sensors
    • ETM9 Trace Module for TI925T Debug
    • Keyboard Matrix Interface (6 x 5 or 8 x 8)
    • Up to Ten MPU General-Purpose I/Os
    • Pulse-Width Tone (PWT) Interface
    • Pulse-Width Light (PWL) Interface
    • Two LED Pulse Generators (LPGs)
    • Real-Time Clock (RTC)
    • LCD Controller With Dedicated System DMA Channel
  • Shared Peripherals
    • Three Universal Asynchronous Receiver/Transmitters (UARTs) (One Supporting SIR Mode for IrDA)
    • Four Interprocessor Mailboxes
    • Up to 14 Shared General-Purpose I/Os
  • Individual Power-Saving Modes for MPU/DSP/TC
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • Two 289-Ball MicroStar BGA™ (Ball Grid Array) Package Options (GZG and GDY Suffixes)

TMS320C55x, C55x, and MicroStar BGA are trademarks of Texas Instruments.
ARM9TDMI is a trademark of ARM Limited.
Thumb is a registered trademark of ARM Limited.
Microwire is a trademark of National Semiconductor Corporation.
1-Wire is a registered trademark of Dallas Semiconductor Corporation.
IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
OMAP and DSP/BIOS are trademarks of Texas Instruments.
Bluetooth is a trademark owned by Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Corporation.
Other trademarks are the property of their respective owners.

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Description

The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices.

The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T ARM core.

The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP/BIOS™ software kernel foundation, and is available in a 289-ball MicroStar BGA package.

The OMAP5910 is targeted at the following applications:

  • Applications processing devices
  • Mobile communications
    • 802.11
    • Bluetooth™ wireless technology
    • GSM (including GPRS and EDGE)
    • CDMA
    • Proprietary government and other
  • Video and image processing (MPEG4, JPEG, Windows® Media Video, etc.)
  • Advanced speech applications (text-to-speech, speech recognition)
  • Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech codecs)
  • Graphics and video acceleration
  • Generalized web access
  • Data processing (fax, encryption/decryption, authentication, signature verification and watermarking)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet OMAP5910 Dual-Core Processor datasheet (Rev. D) Aug. 13, 2004
* Errata OMAP5910 Dual-Core Processor Silicon Errata (Rev. F) Feb. 28, 2006
* Errata OMAP59xx MicroStar BGA Discontinued and Redesigned May 15, 2020
Technical articles Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical articles Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical articles How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018
Technical articles Clove: Low-Power video solutions based on Sitara™ AM57x processors Jul. 21, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

CAD/CAE symbols

Package Pins Download
NFBGA (GVL) 289 View options
NFBGA (ZVL) 289 View options

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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