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  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Military Operating Temperature Range: –55°C to 125°C
  • Industrial Operating Temperature Range: -40°C to 85°C
  • Fast Instruction Cycle Time (30 ns and 40 ns) and 25 ns for Industrial Temp Range
  • Source-Code Compatible With All TMS320C1x and TMS320C2x Devices
  • RAM-Based Operation
    • 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM
    • 1056 × 16-Bit Dual-Access On-Chip Data RAM
  • 2K × 16-Bit On-Chip Boot ROM
  • 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
  • 32-Bit Arithmetic Logic Unit (ALU)
    • 32-bit Accumulator (ACC)
    • 32-Bit Accumulator Buffer (ACCB)
  • 16-Bit Parallel Logic Unit (PLU)
  • 16 × 16-Bit Multiplier, 32-Bit Product
  • 11 Context-Switch Registers
  • Two Buffers for Circular Addressing
  • Full-Duplex Synchronous Serial Port
  • Time-Division Multiplexed Serial Port (TDM)
  • Timer With Control and Counter Registers
  • 16 Software-Programmable Wait-State Generators
  • Divide-by-One Clock Option
  • IEEE 1149.1 Boundary Scan Logic
  • Operations Are Fully Static
  • Enhanced Performance Implanted CMOS (EPIC™) Technology Fabricated by Texas Instruments
  • Packaging
    • 132-Lead Plastic Quad Flat Package (PQ Suffix)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture EPIC is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Military Operating Temperature Range: –55°C to 125°C
  • Industrial Operating Temperature Range: -40°C to 85°C
  • Fast Instruction Cycle Time (30 ns and 40 ns) and 25 ns for Industrial Temp Range
  • Source-Code Compatible With All TMS320C1x and TMS320C2x Devices
  • RAM-Based Operation
    • 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM
    • 1056 × 16-Bit Dual-Access On-Chip Data RAM
  • 2K × 16-Bit On-Chip Boot ROM
  • 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
  • 32-Bit Arithmetic Logic Unit (ALU)
    • 32-bit Accumulator (ACC)
    • 32-Bit Accumulator Buffer (ACCB)
  • 16-Bit Parallel Logic Unit (PLU)
  • 16 × 16-Bit Multiplier, 32-Bit Product
  • 11 Context-Switch Registers
  • Two Buffers for Circular Addressing
  • Full-Duplex Synchronous Serial Port
  • Time-Division Multiplexed Serial Port (TDM)
  • Timer With Control and Counter Registers
  • 16 Software-Programmable Wait-State Generators
  • Divide-by-One Clock Option
  • IEEE 1149.1 Boundary Scan Logic
  • Operations Are Fully Static
  • Enhanced Performance Implanted CMOS (EPIC™) Technology Fabricated by Texas Instruments
  • Packaging
    • 132-Lead Plastic Quad Flat Package (PQ Suffix)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture EPIC is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

The SM320C50-EP digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-µm double-level metal CMOS technology. The C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic C2x architecture give the C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 µ:A. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The SM320C50-EP is available with a clock speed of 66 MHz providing a 30-ns cycle time and a clock speed of 80 MHz providing a 25-ns cycle time.

The SM320C50-EP digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-µm double-level metal CMOS technology. The C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic C2x architecture give the C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 µ:A. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The SM320C50-EP is available with a clock speed of 66 MHz providing a 30-ns cycle time and a clock speed of 80 MHz providing a 25-ns cycle time.

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Type Title Date
* Data sheet SM320C50-EP Digital Signal Processor datasheet (Rev. A) 30 Nov 2005
* VID SM320C50-EP VID V6203613 21 Jun 2016

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