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  • Class B High-Reliability Processing
  • 1-µm CMOS Technology
  • Commercial Operating Temperature Range 0°C to 70°C
  • SM34020APCM40 100-ns Instruction Cycle Time
  • Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)
  • Second-Generation Graphics System Processor (GSP)
    • Object-Code Compatible With the SM34010
    • Enhanced Instruction Set
    • Optimized Graphics Instructions
    • Coprocessor Interface
  • Pixel Processing, XY Addressing, and Window Checking Built Into the Instruction Set
  • Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and Six Arithmetic Pixel Processing Options (Raster Ops)
  • 512-Byte LRU On-Chip Instruction Cache (I-Cache)
  • Optimized DRAM/Video RAM (VRAM) Interface
    • Page Mode for Burst-Memory Operations
    • Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)
    • Byte-Oriented CAS Strobes
  • Flexible Host Processor Interface
    • Supports Host Transfers
    • Direct Access to All of the SM34020APCM40 Address Space
    • Implicit Addressing
    • Prefetch for Enhanced Read Access
  • Programmable CRT Control
    • Composite Synchronization Mode
    • Separate Synchronization Mode
    • Synchronization to External Synchronization
  • Direct Support for Special Features of 1M VRAMs
    • Load Write Mask
    • Load Color Mask
    • Block Write
    • Write Using the Write Mask
  • Flexible Multiprocessor Interface
  • 144-Pin PCM Quad Flat Package (QFP)

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The SM34020APCM40 graphics system processor (GSP) is the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache (I-cache), the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SM34020APCM40 provides user-programmable control of the CRT interface, as well as the memory interface [both standard DRAM and multiport video RAM (VRAM)]. The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16-, and 32-bit-wide pixels.

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Technical documentation

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Type Title Date
* Data sheet SM34020APCM40 datasheet May 09, 2006
Technical article Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical article Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical article How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors Jul. 21, 2016

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QFP (PCM) 144 View options

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