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  • Class B High-Reliability Processing
  • 1-µm CMOS Technology
  • Military Operating Temperature Range
        –55°C to 125°C
  • SMJ34020A-32/40
        125/100-ns Instruction Cycle Time
  • Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)
  • Second-Generation Graphics System Processor
    • Object-Code Compatible With the SMJ34010
    • Enhanced Instruction Set
    • Optimized Graphics Instructions
    • Coprocessor Interface
  • Pixel Processing, XY Addressing, and Window Checking Built Into the Instruction Set
  • Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and Six Arithmetic Pixel Processing Options (Raster Ops)
  • 512-Byte LRU On-Chip Instruction Cache
  • Optimized DRAM/VRAM Interface
    • Page-Mode for Burst Memory Operations
    • Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)
    • Byte-Oriented CAS\ Strobes
  • Flexible Host Processor Interface
    • Supports Host Transfers
    • Direct Access to All of the SMJ34020A Address Space
    • Implicit Addressing
    • Prefetch for Enhanced Read Access
  • Programmable CRT Control
    • Composite Sync Mode
    • Separate Sync Mode
    • Synchronization to External Sync
  • Direct Support for Special Features of 1M VRAMs
    • Load Write Mask
    • Load Color Mask
    • Block Write
    • Write Using the Write Mask
  • Flexible Multi-Processor Interface
  • Packaging Options
    • 145-Pin Grid Array Ceramic Package (GB Suffix)
    • 132-Pin Ceramic Quad Flat Pack (Unformed Lead) (HT Suffix)

  • Class B High-Reliability Processing
  • 1-µm CMOS Technology
  • Military Operating Temperature Range
        –55°C to 125°C
  • SMJ34020A-32/40
        125/100-ns Instruction Cycle Time
  • Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)
  • Second-Generation Graphics System Processor
    • Object-Code Compatible With the SMJ34010
    • Enhanced Instruction Set
    • Optimized Graphics Instructions
    • Coprocessor Interface
  • Pixel Processing, XY Addressing, and Window Checking Built Into the Instruction Set
  • Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and Six Arithmetic Pixel Processing Options (Raster Ops)
  • 512-Byte LRU On-Chip Instruction Cache
  • Optimized DRAM/VRAM Interface
    • Page-Mode for Burst Memory Operations
    • Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)
    • Byte-Oriented CAS\ Strobes
  • Flexible Host Processor Interface
    • Supports Host Transfers
    • Direct Access to All of the SMJ34020A Address Space
    • Implicit Addressing
    • Prefetch for Enhanced Read Access
  • Programmable CRT Control
    • Composite Sync Mode
    • Separate Sync Mode
    • Synchronization to External Sync
  • Direct Support for Special Features of 1M VRAMs
    • Load Write Mask
    • Load Color Mask
    • Block Write
    • Write Using the Write Mask
  • Flexible Multi-Processor Interface
  • Packaging Options
    • 145-Pin Grid Array Ceramic Package (GB Suffix)
    • 132-Pin Ceramic Quad Flat Pack (Unformed Lead) (HT Suffix)

The SMJ34020A graphics system processor (GSP) is the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SMJ34020A provides user-programmable control of the CRT interface as well as the memory interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.

The SMJ34020A graphics system processor (GSP) is the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SMJ34020A provides user-programmable control of the CRT interface as well as the memory interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.

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Type Title Date
* Data sheet SMJ34020A Graphics System Processor datasheet (Rev. D) 16 Sep 2004
* SMD SMJ34020A SMD 5962-91623 21 Jun 2016

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