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  • Military Operating Temperature Range
    • 55°C to 125°C; QML Processing
  • High-Performance Floating-Point Digital Signal Processor (DSP) SMQ320C32-50 (5 V)
    • 40-ns Instruction Cycle Time
    • 275 MOPS
    • 50 MFLOPS
    • 25 MIPS
  • SMQ320C32-60 (5 V)
    • 33-ns Instruction Cycle Time
    • 330 MOPS
    • 60 MFLOPS
    • 30 MIPS
  • 32-Bit High-Performance CPU
  • 16-/ 32-Bit Integer and 32-/ 40-Bit Floating-Point Operations
  • 32-Bit Instruction Word, 24-Bit Addresses
  • Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks
  • Flexible Boot-Program Loader
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port
    • Two 32-Bit Timers
    • Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
  • Enhanced External Memory Interface That Supports 8-/ 16-/ 32-Bit-Wide External RAM for Data Access and Program Execution From 16-/ 32-Bit-Wide External RAM
  • SMJ320C30 and SMJ320C31 Object Code Compatible
  • Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments
  • 144-Pin Plastic Quad Flatpack (PCM Suffix) 5 V
  • Eight Extended-Precision Registers
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • Two- and Three-Operand Instructions
  • Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits
  • Two Sets of Memory Strobes (STRB0\ and STRB1\) and One I/ O Strobe (IOSTRB\) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals
  • Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size
  • STRB0\ and STRB1\ Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes)
  • Multiprocessor Support Through the HOLD\ and HOLDA\ Signals Is Valid for All Strobes

EPIC is a trademark of Texas Instruments Incorporated.

  • Military Operating Temperature Range
    • 55°C to 125°C; QML Processing
  • High-Performance Floating-Point Digital Signal Processor (DSP) SMQ320C32-50 (5 V)
    • 40-ns Instruction Cycle Time
    • 275 MOPS
    • 50 MFLOPS
    • 25 MIPS
  • SMQ320C32-60 (5 V)
    • 33-ns Instruction Cycle Time
    • 330 MOPS
    • 60 MFLOPS
    • 30 MIPS
  • 32-Bit High-Performance CPU
  • 16-/ 32-Bit Integer and 32-/ 40-Bit Floating-Point Operations
  • 32-Bit Instruction Word, 24-Bit Addresses
  • Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks
  • Flexible Boot-Program Loader
  • On-Chip Memory-Mapped Peripherals:
    • One Serial Port
    • Two 32-Bit Timers
    • Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
  • Enhanced External Memory Interface That Supports 8-/ 16-/ 32-Bit-Wide External RAM for Data Access and Program Execution From 16-/ 32-Bit-Wide External RAM
  • SMJ320C30 and SMJ320C31 Object Code Compatible
  • Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments
  • 144-Pin Plastic Quad Flatpack (PCM Suffix) 5 V
  • Eight Extended-Precision Registers
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Two Low-Power Modes
  • Two- and Three-Operand Instructions
  • Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle
  • Block-Repeat Capability
  • Zero-Overhead Loops With Single-Cycle Branches
  • Conditional Calls and Returns
  • Interlocked Instructions for Multiprocessing Support
  • One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits
  • Two Sets of Memory Strobes (STRB0\ and STRB1\) and One I/ O Strobe (IOSTRB\) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals
  • Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size
  • STRB0\ and STRB1\ Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes)
  • Multiprocessor Support Through the HOLD\ and HOLDA\ Signals Is Valid for All Strobes

EPIC is a trademark of Texas Instruments Incorporated.

The SMQ320C32 is a member of the \x92320C3x generation of digital signal processors from Texas Instruments. The SMQ320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-um triple-level-metal CMOS technology. The enhancements to the \x92320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts.

The internal busing and special digital signal processing instruction set of the SMQ320C32 have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SMQ320C32 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.

The SMQ320C32 is a member of the \x92320C3x generation of digital signal processors from Texas Instruments. The SMQ320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-um triple-level-metal CMOS technology. The enhancements to the \x92320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts.

The internal busing and special digital signal processing instruction set of the SMQ320C32 have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SMQ320C32 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.

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Technical documentation

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Type Title Date
* Data sheet SMQ320C32 Digital Signal Processor datasheet (Rev. C) 12 Oct 2001
Application note 320C3x, 320C4x, and 320MCM42x Power-Up Sensitivity at Cold Temperatures (Rev. D) 06 Aug 2004
More literature SMQ320C32 / 5962-9679001NXB DSP (Rev. D) 02 Apr 2001
Application note Interfacing Memory to the TMS320C32 DSP (Rev. A) 01 May 1996
Application note FIFO Synchronous Retransmit: Programmable DSP-Interface for FIR Filtering (Rev. A) 01 Mar 1996
Application note Interfacing TI Clocked FIFOs With TI Floating-Point DSPs (Rev. A) 01 Mar 1996
Application note How TMS320 Tools Interact With the TMS320C32's Enhanced Memory Interface 01 Nov 1995
Application note Engine Knock Detection Using Spectral Analysis With TMS320C25 or TMS320C30 DSPs 01 Jan 1995
User guide JTAG/MPSD Emulation Technical Reference (Rev. A) 01 Dec 1994
Application note Setting Up TMS320 DSP Interrupts in 'C' 01 Nov 1994
User guide TMS320C3x Workstation Emulator Installation Guide 01 Nov 1994

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