Product details


Technology Family TTL Applications GTL Bits (#) 8 IOH (Max) (mA) -15 IOL (Max) (mA) 48 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators


  • 10KH Compatible
  • ECL Clock and TTL Control Inputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
  • Package Options Include "Small Outline" Packages and Standard Plastic DIPs
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This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.

The SN10KHT5574 is characterized for operation from 0°C to 75°C.

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Technical documentation

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Type Title Date
* Datasheet Octal ECL-to-TTL Translator w/D-Type Edge-Triggered FF & 3-State Outputs datasheet Oct. 01, 1990
Selection guides Voltage translation buying guide Jun. 13, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

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