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Product details

Parameters

Technology Family HCT Function Decoder/Demultiplexer Configuration 3:8 Channels (#) 1 VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type CMOS open-in-new Find other Encoders & decoders

Package | Pins | Size

CDIP (J) 16 CFP (W) 16 LCCC (FK) 20 open-in-new Find other Encoders & decoders

Features

  • Operating Voltage Range of 4.5 V to 5.5 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 17 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
  • Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

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Description

The ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G)\ and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54HCT138, SN74HCT138 datasheet (Rev. E) Sep. 15, 2003
* SMD SN54HCT138 SMD 85504012A Jun. 21, 2016
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
CFP (W) 16 View options
LCCC (FK) 20 View options

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