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The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer datasheet (Rev. B) | PDF | HTML | Nov 19, 2014 |
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | Oct 17, 2007 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
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