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SN65EPT23

ACTIVE

3.3-V ecl differential receiver

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Data sheet

SN65EPT23

ACTIVE
Data sheet Order now

Product details

Function Receiver, Translator Protocols LVDS, LVPECL Number of transmitters 0 Number of receivers 2 Signaling rate (Mbps) 600 Input signal LVDS, LVPECL Output signal CMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Translator Protocols LVDS, LVPECL Number of transmitters 0 Number of receivers 2 Signaling rate (Mbps) 600 Input signal LVDS, LVPECL Output signal CMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • Dual 3.3 V Differential LVPECL/LVDS to
    LVTTL/LVCMOS Buffer Translator
  • 24 mA LVTTL Ouputs
  • Operating Range
    • VCC = 3.0 V to 3.6 V
    • GND = 0 V
  • Support for Clock Frequencies > 300 MHz
  • 2.0 ns Typical Propagation Delay
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100EPT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • Dual 3.3 V Differential LVPECL/LVDS to
    LVTTL/LVCMOS Buffer Translator
  • 24 mA LVTTL Ouputs
  • Operating Range
    • VCC = 3.0 V to 3.6 V
    • GND = 0 V
  • Support for Clock Frequencies > 300 MHz
  • 2.0 ns Typical Propagation Delay
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100EPT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left open. The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.

The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left open. The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 3.3-V ECL Differential Receiver datasheet (Rev. A) Jan 27, 2011
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct 17, 2007

Design & development

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Simulation model

SN65EPT23 IBIS Model

SLLM146.ZIP (16 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VSSOP (DGK) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
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