The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation.
The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 3.3 V Dual LVTTL to Differential LVPECL Translator datasheet | Dec 12, 2008 | |
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | Oct 17, 2007 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
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