SN65LVELT22

ACTIVE

3.3-V dual LVTTL to differential LVPECL translator

Product details

Function Driver, Translator Protocols LVPECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (MBits) 3500 Input signal LVTTL Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver, Translator Protocols LVPECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (MBits) 3500 Input signal LVTTL Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • 450 ps (typ) Propagation Delay
  • Operating Range: VCC 3.0 V to 3.8 with
    GND = 0 V
  • <50 ps (max) Output to Output Skew
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100LVELT22
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • 450 ps (typ) Propagation Delay
  • Operating Range: VCC 3.0 V to 3.8 with
    GND = 0 V
  • <50 ps (max) Output to Output Skew
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100LVELT22
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation.

The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.

The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation.

The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.

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Type Title Date
* Data sheet 3.3 V Dual LVTTL to Differential LVPECL Translator datasheet 12 Dec 2008
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 17 Oct 2007

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