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SN65LVELT23

ACTIVE

3.3-V dual differential LVPECL buffer to LVTTL translator

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Data sheet

SN65LVELT23

ACTIVE
Data sheet Order now

Product details

Function Receiver, Translator Protocols LVDS, LVPECL Number of transmitters 0 Number of receivers 2 Signaling rate (Mbps) 600 Input signal LVDS, LVPECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Translator Protocols LVDS, LVPECL Number of transmitters 0 Number of receivers 2 Signaling rate (Mbps) 600 Input signal LVDS, LVPECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator
  • 24-mA LVTTL Ouputs
  • Operating Range
    • PECL VCC = 3 V to 3.6 V With GND = 0 V
  • Support for Clock Frequencies to >180 MHz
  • 2-ns Typical Propagation Delay
  • Internal Input Pullup and Pulldown Resistors
  • Built-in Temperature Compensation
  • Drop-In Compatible to MC100LVELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator
  • 24-mA LVTTL Ouputs
  • Operating Range
    • PECL VCC = 3 V to 3.6 V With GND = 0 V
  • Support for Clock Frequencies to >180 MHz
  • 2-ns Typical Propagation Delay
  • Internal Input Pullup and Pulldown Resistors
  • Built-in Temperature Compensation
  • Drop-In Compatible to MC100LVELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open. The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.

The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open. The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.
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SN65LVELT22 ACTIVE 3.3-V dual LVTTL to differential LVPECL translator Driver variant

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 3.3V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator datasheet (Rev. A) Aug 3, 2009
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct 17, 2007

Design & development

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Simulation model

SN65LVELT23 IBIS Model

SLLM416.ZIP (22 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
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