Product details


Function Decoder, Demultiplexer Technology Family TTL VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 1 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 75 ICC @ nom voltage (Max) (mA) 70 tpd @ nom Voltage (Max) (ns) 50 Configuration 4:10 Product type Standard IOL (Max) (mA) 80 IOH (Max) (mA) -20 Rating Catalog Operating temperature range (C) 0 to 70 Bits (#) 10 Digital input leakage (Max) (uA) 5 ESD CDM (kV) 0.75 ESD HBM (kV) 2 open-in-new Find other Encoders & decoders

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 open-in-new Find other Encoders & decoders






  • Full Decoding of Input Logic
  • 80-mA Sink-Current Capability
  • All Outputs Are Off for Invalid BCD Input Conditions


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These monolithic BCD-to-decimal decoders/drivers consist of eight inverters and ten four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outputs remain off for all invalid binary input conditions. These decoders feature TTL inputs and high-performance, n-p-n output transistors designed for use as indicator/relay drivers or as open-collector logic-circuit drivers. Each of the high-breakdown output transistors (30 volts) will sink up to 80 milliamperes of current. Each input is one normalized Series 54 /74 load. Inputs and outputs are entirely compatible for use with TTL logic circuits, and the outputs are compatible for interfacing with most MOS integrated circuits. Power dissipation is typically 215 milliwatts.


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Technical documentation

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Type Title Date
* Datasheet BCD-to-Decimal Decoders/Drivers datasheet Mar. 01, 1988
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options

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