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Product details

Parameters

Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 10 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 90 ICC @ nom voltage (Max) (mA) 0.04 Propagation delay (Max) (ns) 0 Operating temperature range (C) -40 to 85 open-in-new Find other Bus-termination arrays

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other Bus-termination arrays

Features

  • Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems
  • Reduces Undershoot and Overshoot Caused By Line Reflections
  • Repetitive Peak Forward Current . . . IFRM = 100 mA
  • Inputs Are TTL-Voltage Compatible
  • Low Power Consumption (Like CMOS)
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise
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Description

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1071 prevents bus lines from floating without using pullup or pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.

The SN74ACT1071 is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Datasheet 10-Bit Bus-Termination Array With Bus-Hold Function datasheet Apr. 01, 1993
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options

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