Product details

Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 50 Features Programmable Flags, Unidirectional
Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 50 Features Programmable Flags, Unidirectional
SSOP (DL) 56 191 mm² 18.42 x 10.35
  • Member of the Texas Instruments WidebusTM Family
  • Load Clock and Unload Clock Can Be Asynchronous or Coincident
  • 256 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Full, Empty, and Half-Full Flags
  • Programmable Almost-Full/Almost-Empty Flag
  • Fast Access Times of 15 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 50 MHz
  • 3-State Outputs
  • Pin-to-Pin Compatible With SN74ACT7804 and SN74ACT7814
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus is a trademark of Texas Instruments Incorporated.

  • Member of the Texas Instruments WidebusTM Family
  • Load Clock and Unload Clock Can Be Asynchronous or Coincident
  • 256 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Full, Empty, and Half-Full Flags
  • Programmable Almost-Full/Almost-Empty Flag
  • Fast Access Times of 15 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 50 MHz
  • 3-State Outputs
  • Pin-to-Pin Compatible With SN74ACT7804 and SN74ACT7814
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus is a trademark of Texas Instruments Incorporated.

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7806 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.

Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the full (FULL\), empty (EMPTY\), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL\ output is low when the memory is full and high when the memory is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN\) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 - Y) words.

A low level on the reset (RESET\) input resets the internal stack pointers and sets FULL\ high, HF low, and EMPTY\ low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE\) input is high.

The SN74ACT7806 is characterized for operation from 0°C to 70°C.

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7806 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.

Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the full (FULL\), empty (EMPTY\), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL\ output is low when the memory is full and high when the memory is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN\) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 - Y) words.

A low level on the reset (RESET\) input resets the internal stack pointers and sets FULL\ high, HF low, and EMPTY\ low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE\) input is high.

The SN74ACT7806 is characterized for operation from 0°C to 70°C.

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Technical documentation

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Type Title Date
* Data sheet 256 X 18 Strobed First-In, First-Out Memory datasheet (Rev. C) 01 Apr 1998
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996
Application note FIFO Memories: Solutions For Increasing Clock Rates And Data Widths (Rev. A) 01 Mar 1996
Application note Power-Dissipation Calculations for TI FIFO Products (Rev. A) 01 Mar 1996

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