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Product details

Parameters

Technology Family ALS Function Decoder, Demultiplexer Configuration 3:8 Channels (#) 1 VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type TTL open-in-new Find other Encoders & decoders

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Encoders & decoders

Features

  • Combines Decoder and 3-Bit Address Latch
  • Incorporates Two Output Enables to Simplify Cascading
  • Package Options Include Plastic Small- Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
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Description

The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable () input is low, the devices act as decoders/demultiplexers. When goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as remains high. The output-enable controls (G1 and G2\) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2\ is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.

The SN54ALS137A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS137A and SN74AS137 are characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

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Type Title Date
* Datasheet 3-Line To 8-Line Decoders/Demultiplexers With Address Latches datasheet (Rev. C) Jan. 01, 1995
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options

Ordering & quality

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