Product details


Technology Family AS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 2 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 125 ICC @ nom voltage (Max) (mA) 35 tpd @ nom Voltage (Max) (ns) 12 IOL (Max) (mA) 20 IOH (Max) (mA) -2 Function Parity Product type Other Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other Counter, arithmetic & parity function ICs


  • Generate Either Odd or Even Parity for Nine Data Lines
  • Cascadable for n-Bit Parity
  • Can Be Used to Upgrade Existing Systems Using MSI Parity Circuits
  • Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs
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These universal 9-bit parity generators/checkers utilize advanced Schottky high-performance

circuitry and feature odd ( ODD) and even ( EVEN) outputs to facilitate operation of either odd- or even-parity applications. The word-length capability is easily expanded by cascading.

These devices can be used to upgrade the performance of most systems utilizing the SN74ALS180 and SN74AS180 parity generators/checkers. Although the SN74ALS280 and SN74AS280 are implemented without expander inputs, the corresponding function is provided by the availability of an input (I) at terminal 4 and the absence of any internal connection at terminal 3. This permits the SN74ALS280 and SN74AS280 to be substituted for the SN74ALS180 and SN74AS180 in existing designs to produce an identical function even if the devices are mixed with existing SN74ALS180 and SN74AS180 devices.

All SN74AS280 inputs are buffered to lower the drive requirements.

The SN74ALS280 and SN74AS280 are characterized for operation from 0°C to 70°C.



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Technical documentation

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Type Title Date
* Datasheet 9-Bit Parity Generators/Checkers datasheet (Rev. C) Dec. 01, 1994
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Advanced Schottky Load Management Feb. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options

Ordering & quality

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