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Product details

Parameters

Technology Family F Function Decoder, Demultiplexer Configuration 3:8 Channels (#) 1 VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 open-in-new Find other Encoders & decoders

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 open-in-new Find other Encoders & decoders

Features

  • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
  • Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
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Description

The ´F138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN54F138 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F138 is characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 10
Type Title Date
* Datasheet 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. B) Jul. 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options

Ordering & quality

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