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Product details

Parameters

Technology Family F VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 2 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 70 ICC @ nom voltage (Max) (mA) 35 tpd @ nom Voltage (Max) (ns) 11 IOL (Max) (mA) 20 IOH (Max) (mA) -1 Function Parity Product type Other Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Generates Either Odd or Even Parity for Nine Data Lines
  • Cascadable for N-Bits Parity
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
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Description

These universal, monolithic, 9-bit parity generators/checkers feature odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading.

The SN54F280B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F280B is characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

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Type Title Date
* Datasheet 9-Bit Parity Generators/Checkers datasheet (Rev. A) Oct. 01, 1993
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

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