Product details

Technology Family HC Function Encoder Configuration 8:3, 10:4 Number of channels (#) 1 Operating temperature range (C) -40 to 85 Rating Catalog
Technology Family HC Function Encoder Configuration 8:3, 10:4 Number of channels (#) 1 Operating temperature range (C) -40 to 85 Rating Catalog
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 80-µA max ICC
  • Typical tpd = 16ns
  • ±4-mA output drive at 5V
  • Low input current of 1µA max
  • Encode eight data lines to 3-line binary (Octal)
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 80-µA max ICC
  • Typical tpd = 16ns
  • ±4-mA output drive at 5V
  • Low input current of 1µA max
  • Encode eight data lines to 3-line binary (Octal)

The SNx4HC148 is an 8-input priority encoder. Added input enable (EI) and output enable (EO) signals allow for cascading multiple stages without added external circuitry.

The SNx4HC148 is an 8-input priority encoder. Added input enable (EI) and output enable (EO) signals allow for cascading multiple stages without added external circuitry.

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Technical documentation

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Type Title Date
* Data sheet SNx4HC148 8-Line to 3-Line Priority Encoders datasheet (Rev. H) PDF | HTML 02 Mar 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options

Ordering & quality

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