The ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G)\ and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
| Type | Title | Date | |
|---|---|---|---|
| * | Data sheet | SN54HCT138, SN74HCT138 datasheet (Rev. E) | 15 Sep 2003 |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | |
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | |
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | |
| User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | |
| More literature | Logic Cross-Reference (Rev. A) | 07 Oct 2003 | |
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | |
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | |
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | |
| Application note | SN54/74HCT CMOS Logic Family Applications and Restrictions | 01 May 1996 | |
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
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| SOIC (D) | 16 | View options |
| TSSOP (PW) | 16 | View options |
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