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Product details

Parameters

Function Encoder, Multiplexer Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 1 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 35 ICC @ nom voltage (Max) (mA) 25 tpd @ nom Voltage (Max) (ns) 35 Configuration 8:3 Product type 3-State Output IOL (Max) (mA) 24 IOH (Max) (mA) -2.6 Rating Catalog Operating temperature range (C) 0 to 70 Bits (#) 8 Digital input leakage (Max) (uA) 5 ESD CDM (kV) 0.75 ESD HBM (kV) 2 open-in-new Find other Encoders & decoders

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Encoders & decoders

Features

  • 3-State Outputs Drive Bus Lines Directly
  • Encodes 8 Data Lines to 3-Line Binary (Octal)
  • Applications Include:
    • N-Bit Encoding
    • Code Converters and Generators
  • Typical Data Delay … 15 ns
  • Typical Power Dissipation … 60 mW

 

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Description

These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The 'LS348 circuits encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion. Outputs A0, A1, and A2 are implemented in three-state logic for easy expansion up to 64 lines without the need for external circuitry. See Typical Application Data.

 

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Technical documentation

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Type Title Date
* Datasheet 8-Line To 3-Line Priority Encoders With 3-State Outputs datasheet Mar. 01, 1988
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options

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