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Product details

Parameters

Channels (#) 8 Technology Family LS VCC (Min) (V) 4.85 VCC (Max) (V) 5.25 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10-50ns) open-in-new Find other Digital comparator

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 open-in-new Find other Digital comparator

Features

  • Compares Two-8-Bit Words
  • Choice of Totem-Pole or Open-Collector Outputs
  • Hysteresis at P and Q Inputs
  • 'LS682 has 20-k Pullup Resistors on the Q Inputs
  • SN74LS686 and 'LS687 … JT and NT 24-Pin, 300-Mil Packages
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Description

These magnitude comparators perform comparisons of two eight-bit binary or BCD words. All types provide P = Q\ outputs and all except 'LS688 provide P > Q\ outputs as well. The 'LS682, 'LS684, 'LS686, and 'LS688 have totem-pole outputs, while the 'LS685 and 'LS687 have open-collector outputs. The 'LS682 features 20-k pullup termination resistors on the Q inputs for analog or switch data.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 8-Bit Magnitude/Identity Comparators datasheet Mar. 01, 1988
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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