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SN74LV138A

ACTIVE

Three-line to eight-line decoders/demultiplexers

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Data sheet

SN74LV138A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Number of channels 1 Operating temperature range (°C) -40 to 125, -40 to 85 Rating Catalog Supply current (max) (µA) 20
Technology family LV-A Number of channels 1 Operating temperature range (°C) -40 to 125, -40 to 85 Rating Catalog Supply current (max) (µA) 20
SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4 VQFN (RGY) 16 14 mm² 4 x 3.5 WQFN (BQB) 16 8.75 mm² 3.5 x 2.5
  • VCC operation of 2 V to 5.5 V
  • Maximum tpd of 9.5 ns at 5 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • VCC operation of 2 V to 5.5 V
  • Maximum tpd of 9.5 ns at 5 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV138A device is 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCC operation.

The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2, G0, G1) select one of eight output lines. The two active-low (G0, G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding.

The SN74LV138A device is 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCC operation.

The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2, G0, G1) select one of eight output lines. The two active-low (G0, G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding.
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Technical documentation

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* Data sheet SN74LV138A 3-Line to 8-Line Decoders or Demultiplexers datasheet (Rev. N) PDF | HTML 15 Mar 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV138A IBIS Model

SCEM129.ZIP (16 KB) - IBIS Model
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Package Pins Download
SOIC (D) 16 View options
SOP (NS) 16 View options
SSOP (DB) 16 View options
TSSOP (PW) 16 View options
TVSOP (DGV) 16 View options
VQFN (RGY) 16 View options
WQFN (BQB) 16 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

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