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Product details

Parameters

Technology Family LV-A Function Decoder, Demultiplexer Configuration 3:8 Channels (#) 1 VCC (Min) (V) 2 VCC (Max) (V) 5.5 Input type LVTTL/CMOS Output type CMOS open-in-new Find other Encoders & decoders

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 SSOP (DB) 16 48 mm² 6.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 TSSOP (PW) 16 22 mm² 5 x 4.4 TVSOP (DGV) 16 23 mm² 3.6 x 6.4 VQFN (RGY) 16 14 mm² 4 x 3.5 open-in-new Find other Encoders & decoders

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 9.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

The 'LV138A devices are 3-line to 8-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation.

These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Technical documentation

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Type Title Date
* Datasheet SN54LV138A, SN74LV138A datasheet (Rev. L) Aug. 23, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARD Download
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODEL Download
SCEM129.ZIP (16 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SO (NS) 16 View options
SOIC (D) 16 View options
SSOP (DB) 16 View options
TSSOP (PW) 16 View options
TVSOP (DGV) 16 View options
VQFN (RGY) 16 View options

Ordering & quality

Information included:
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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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