Product details

Technology Family LV-A Number of channels (#) 2 Operating temperature range (C) -40 to 85 Rating Catalog ICC (Max) (uA) 20
Technology Family LV-A Number of channels (#) 2 Operating temperature range (C) -40 to 85 Rating Catalog ICC (Max) (uA) 20
SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 SSOP (DB) 16 33 mm² 5.3 x 6.2 TSSOP (PW) 16 22 mm² 4.4 x 5 VQFN (RGY) 16 14 mm² 4 x 3.5
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7.5 ns at 5 V
  • Support Mixed-Mode Voltage Operation on All Ports
  • Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7.5 ns at 5 V
  • Support Mixed-Mode Voltage Operation on All Ports
  • Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation.

These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The ’LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation.

These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Technical documentation

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* Data sheet SN54LV139A, SN74LV139A datasheet (Rev. I) 04 Apr 2005

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Not available on TI.com
Simulation model

SN74LV139A IBIS Model SN74LV139A IBIS Model

Package Pins Download
SO (NS) 16 View options
SOIC (D) 16 View options
SSOP (DB) 16 View options
TSSOP (PW) 16 View options
VQFN (RGY) 16 View options

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