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Product details

Parameters

Technology Family LV-A Function Encoder, Multiplexer Configuration 2:1 Channels (#) 4 VCC (Min) (V) 2 VCC (Max) (V) 5.5 Input type LVTTL/CMOS Output type CMOS open-in-new Find other Encoders & decoders

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 SSOP (DB) 16 48 mm² 6.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 TVSOP (DGV) 16 23 mm² 3.6 x 6.4 open-in-new Find other Encoders & decoders

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at VCC, TA = 25°C
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

The ’V157A devices are quadruple 2-line to 1-line data selectors/multiplexers designed for 2-V to 5.5-V VCC operation.

These devices contain inverters and drivers to supply full data selection to the four output gates. A separate strobe (G)\ input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The ’LV157A devices present true data.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Technical documentation

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Type Title Date
* Datasheet SN54LV157A, SN74LV157A datasheet (Rev. F) Apr. 21, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCLM121.ZIP (41 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SO (NS) 16 View options
SOIC (D) 16 View options
SSOP (DB) 16 View options
TSSOP (PW) 16 View options
TVSOP (DGV) 16 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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