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Product details

Parameters

DSP 1 C64x On-chip L2 cache/RAM 1024 KB Total on-chip memory (KB) 1056 DRAM SDRAM PCI/PCIe 1 PCI Serial I/O McBSP Operating temperature range (C) -40 to 105, 0 to 90 Rating Catalog open-in-new Find other C6000 floating-point DSPs

Package | Pins | Size

FCBGA (GLZ) 532 529 mm² 23 x 23 FCBGA (ZLZ) 532 529 mm² 23 x 23 open-in-new Find other C6000 floating-point DSPs

Features

  • Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Twenty-Eight Operations/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C62x™
    • C6414/15/16 Devices Pin-Compatible
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Non-Aligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • Viterbi Decoder Coprocessor (VCP) [C6416]
    • Supports Over 600 7.95-Kbps AMR
    • Programmable Code Parameters
  • Turbo Decoder Coprocessor (TCP) [C6416]
    • Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
  • Two External Memory Interfaces (EMIFs)
    • One 64-Bit (EMIFA), One 16-Bit (EMIFB)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1280M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32-/16-Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
    • Three PCI Bus Address Registers:
         Prefetchable Memory
         Non-Prefetchable Memory I/O
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching-, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola™)
  • Three 32-Bit General-Purpose Timers
  • Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
  • 3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414, TMS320C6415, and TMS320C6416 shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416.
These C64xdevices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

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Description

The TMS320C64x™ DSPs (including the TMS320C6414, TMS320C6415, and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™ developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 600 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to forty-three 384-Kbps or seven 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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Type Title Date
* Datasheet TMS320C6414, TMS320C6415, TMS320C6416 Fixed-Point Digital Signal Processors datasheet (Rev. N) May 26, 2005
* Errata TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) (Rev. T) Aug. 01, 2007
Application notes How to Migrate CCS 3.x Projects to the Latest CCS Feb. 06, 2020
User guides Emulation and Trace Headers Technical Reference Manual (Rev. I) Aug. 09, 2012
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320C6000 Programmer's Guide (Rev. K) Jul. 11, 2011
User guides TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) Jul. 30, 2010
User guides TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) Jul. 02, 2009
Application notes Migrating from TMS320C6416/15/14 to TMS320C6416T/15T/14T (Rev. B) Feb. 22, 2008
Application notes TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) Sep. 04, 2007
User guides TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) Apr. 11, 2007
More literature TMS320C6000 DSP TCP/IP Stack Software (Rev. C) Apr. 04, 2007
User guides TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) Jan. 25, 2007
User guides TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) Dec. 14, 2006
User guides TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) Nov. 15, 2006
Application notes Using TMS320C6416 Coprocessors: Turbo Coprocessor (TCP) (Rev. B) Aug. 22, 2006
User guides TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) Feb. 28, 2006
User guides TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) Jan. 01, 2006
Application notes TMS320C6416 DSP Hardware Designer's Resource Guide (Rev. B) Oct. 25, 2005
Application notes Migrating from TMS320C64x to TMS320C64x+ (Rev. A) Oct. 20, 2005
Application notes TMS320C6000 EMIF to USB Interfacing Using Cypress EZ-USB SX2 (Rev. A) May 20, 2005
User guides TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) Mar. 01, 2005
User guides TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) Jan. 25, 2005
Application notes Migrating From TMS320C6416/15/14/11 Rev 1.1 to Rev 2.0 Oct. 19, 2004
User guides TMS320C64x DSP Turbo-Decoder Coprocessor (TCP) Reference Guide (Rev. B) Sep. 20, 2004
User guides TMS320C64x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide (Rev. D) Sep. 20, 2004
Application notes Use and Handling of Semiconductor Packages With ENIG Pad Finishes Aug. 31, 2004
User guides TMS320C6000 Chip Support Library API Reference Guide (Rev. J) Aug. 13, 2004
User guides TMS320C64x DSP Universal Test and Operations PHY Interface for ATM (UTOPIA) RG (Rev. A) Jun. 11, 2004
Application notes TMS320C64x Reference Design May 12, 2004
Application notes TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) Apr. 26, 2004
User guides TMS320C6000 DSP/BIOS 4.90 Application Programming Interface (API) Ref Guide (Rev. G) Apr. 22, 2004
Application notes TMS320C6000 Board Design: Considerations for Debug (Rev. C) Apr. 21, 2004
User guides TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) Mar. 25, 2004
Application notes TMS320C6000 McBSP Initialization (Rev. C) Mar. 08, 2004
Application notes TMS320C6000 EDMA IO Scheduling and Performance Mar. 05, 2004
Application notes TMS320C64x EDMA Performance Data Mar. 05, 2004
Application notes TMS320C64x EDMA Architecture Mar. 03, 2004
Application notes TMS320C6416 Power-On Self Test (Rev. A) Feb. 06, 2004
Application notes TMS320C6416 Coprocessors and Bit Error Rates Nov. 07, 2003
Application notes TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance Oct. 31, 2003
Application notes Tips for Using the EDMA with the Utopia Port Sep. 15, 2003
Application notes Using TMS320C6416 Coprocessors: Viterbi Coprocessor (VCP) (Rev. D) Sep. 15, 2003
Application notes Migrating from TMS320C6416 to TMS320TCI100 (Rev. A) Aug. 15, 2003
User guides TMS320C6000 DSP Designing for JTAG Emulation Reference Guide Jul. 31, 2003
Application notes TMS320C6414/5/6 Power Consumption Summary (Rev. C) Jun. 30, 2003
Application notes A DSP/BIOS AIC23 Codec Device Driver for the TMS320C6416 DSK (Rev. A) Jun. 01, 2003
User guides TMS320C6000 DSP Cache User's Guide (Rev. A) May 05, 2003
Application notes Using IBIS Models for Timing Analysis (Rev. A) Apr. 15, 2003
Application notes How to Begin Development Today With the TMS320C6414, C6415, and C6416 DSPs (Rev. A) Mar. 06, 2003
More literature TMS320TCI1x UMTS Chipset Product Bulletin Jan. 30, 2003
More literature Network Video Developer's Kit Product Bulletin Jul. 23, 2002
Application notes TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) Jun. 04, 2002
User guides TMS320C6416 Seamless CVE Model User's Guide (Rev. B) May 30, 2002
Application notes TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) Apr. 17, 2002
Application notes TMS320C6000 Board Design for JTAG (Rev. C) Apr. 02, 2002
Application notes TMS320C6000 EMIF to External Flash Memory (Rev. A) Feb. 13, 2002
Application notes Cache Usage in High-Performance DSP Applications with the TMS320C64x Dec. 13, 2001
Application notes Using a TMS320C6000 McBSP for Data Packing (Rev. A) Oct. 31, 2001
Application notes TMS320C6000 Enhanced DMA: Example Applications (Rev. A) Oct. 24, 2001
Application notes Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) Sep. 30, 2001
Application notes TMS320C6000 Host Port to MC68360 Interface (Rev. A) Sep. 30, 2001
Application notes TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) Aug. 31, 2001
Application notes TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) Aug. 31, 2001
Application notes Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) Aug. 31, 2001
Application notes TMS320C6000 System Clock Circuit Example (Rev. A) Aug. 15, 2001
Application notes TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) Jul. 23, 2001
Application notes TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) Jul. 10, 2001
Application notes TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) Jun. 30, 2001
Application notes TMS320C6000 Host Port to MPC860 Interface (Rev. A) Jun. 21, 2001
Application notes TMS320C6000 McBSP: IOM-2 Interface (Rev. A) May 21, 2001
Application notes TMS320C6415/6416: Using PCI EEPROM Interface and McBSP2 in a Single System Mar. 01, 2001
User guides TMS320C64x Technical Overview (Rev. B) Jan. 30, 2001
Application notes Circular Buffering on TMS320C6000 (Rev. A) Sep. 12, 2000
Application notes TMS320C6000 McBSP as a TDM Highway (Rev. A) Sep. 11, 2000
Application notes TMS320C6000 u-Law and a-Law Companding with Software or the McBSP Feb. 02, 2000
Application notes General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point Jan. 31, 2000
Application notes TMS320C6000 C Compiler: C Implementation of Intrinsics Dec. 07, 1999
Application notes TMS320C6000 McBSP: I2S Interface Sep. 08, 1999

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$512.47
Description

The TMS320C6416 DSP Starter Kit (DSK) developed jointly with Spectrum Digital is a low-cost development platform designed to speed the development of high performance applications based on TI´s TMS320C64x DSP generation. The kit uses USB communications for true plug-and-play (...)

Features

The DSK features the TMS320C6416 DSP, a 1 GHz device delivering up to 8000 million instructions per second (MIPs) and is designed for products that require the highest performing DSPs. The C6416 is based on the high performing TMS320C6400 DSP platform designed to needs of high-performing (...)

Software development

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$995.00
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$1,495.00
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TMS320C6000 Chip Support Library
SPRC090 — The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)
DRIVERS & LIBRARIES Download
C62x/C64x Fast Run-Time Support (RTS) Library
SPRC122 The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
DRIVERS & LIBRARIES Download
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
DRIVERS & LIBRARIES Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
Features
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)
SOFTWARE CODECS Download
Adaptive Digital Technologies DSP VOIP, speech and audio codecs
Provided by Adaptive Digital Technologies, Inc. — Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide solutions (...)
SOFTWARE CODECS Download
CouthIT DSP VoIP, speech, and audio codecs
Provided by Couth Infotech Pvt. Ltd. — Since 1999, CouthIT has been helping customers transform their ideas into real-time robust software solutions. They license specialized, pre-built, highly optimized software modules in the areas of VoIP and speech and audio codecs, and provide software optimization and customization services for (...)
SOFTWARE CODECS Download
Vocal technologies DSP VoIP codecs
Provided by VOCAL Technologies, Ltd. — With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM039D.ZIP (85 KB) - IBIS Model
SIMULATION MODELS Download
SPRM043C.ZIP (11 KB) - BSDL Model
SIMULATION MODELS Download
SPRM138.ZIP (11 KB) - BSDL Model
SCHEMATICS Download
SPRC137.ZIP (3442 KB)
SCHEMATICS Download
SPRC138.ZIP (10 KB)

CAD/CAE symbols

Package Pins Download
FCBGA (GLZ) 532 View options
FCBGA (ZLZ) 532 View options

Ordering & quality

Support & training

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