TMS320F280220 Piccolo Microcontroller | TI.com

TMS320F280220 (NRND) Piccolo Microcontroller

Piccolo Microcontroller - TMS320F280220
Datasheet
TMS320F2802x0 Piccolo Microcontrollers datasheet (Rev. B)
Errata
 

Not Recommended for New Designs (NRND)

Replaced By TMS320F28022 – The device has the SAME FUNCTIONALITY and PINOUT as the compared device but is NOT an exact equivalent.

TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.

Description

The F2802x0 Piccolo family of microcontrollers provides the power of the C28x core coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

Features

  • Highlights
    • High-Efficiency 32-Bit CPU (TMS320C28x)
    • 50-MHz and 40-MHz Devices
    • Single 3.3-V Supply
    • Integrated Power-on Resets and Brown-out Resets
    • Two Internal Zero-pin Oscillators
    • Up to 22 Multiplexed GPIO Pins
    • Three 32-Bit CPU Timers
    • On-Chip Flash, SARAM, OTP Memory
    • Code-security Module
    • Serial Port Peripherals (SCI/SPI/I2C)
    • Enhanced Control Peripherals
      • Up to 3 Enhanced Pulse Width Modulator (ePWM) Modules for up to 6 Channels
      • Enhanced Capture (eCAP) Module
      • Analog-to-Digital Converter (ADC)
      • On-Chip Temperature Sensor
      • Up to 2 Comparators (280270 Only)
    • 38-Pin and 48-Pin Packages
  • High-Efficiency 32-Bit CPU (TMS320C28x)
    • 50 MHz (20-ns Cycle Time)
    • 40 MHz (25-ns Cycle Time)
    • 16 x 16 and 32 x 32 MAC Operations
    • 16 x 16 Dual MAC
    • Harvard Bus Architecture
    • Atomic Operations
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • Code-Efficient (in C/C++ and Assembly)
  • Endianness: Little Endian
  • Low Device and System Cost:
    • Single 3.3-V Supply
    • No Power Sequencing Requirement
    • Integrated Power-on and Brown-out Resets
    • Small Packaging, as Low as 38-Pin Available
    • Low Power
    • No Analog Support Pins
  • Clocking:
    • Two Internal Zero-pin Oscillators
    • On-Chip Crystal Oscillator/External Clock Input
    • Dynamic PLL Ratio Changes Supported
    • Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • Up to 22 Individually Programmable, Multiplexed GPIO Pins With Input Filtering
  • Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts
  • Three 32-Bit CPU Timers
  • Independent 16-Bit Timer in Each ePWM Module
  • On-Chip Memory
    • Flash, SARAM, OTP, Boot ROM Available
  • 128-Bit Security Key and Lock
    • Protects Secure Memory Blocks
    • Prevents Firmware Reverse Engineering
  • Serial Port Peripherals
    • One SCI (UART) Module
    • One SPI Module
    • One Inter-Integrated-Circuit (I2C) Bus
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug via Hardware
  • 2802x0 Packages
    • 38-Pin DA Thin Shrink Small-Outline Package (TSSOP)
    • 48-Pin PT Low-Profile Quad Flatpack (LQFP)