ADC32RF83

Name: ADC32RF83
Brand: TI
SKU: ADC32RF83
Price: 1060.88 USD

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Zwei-Kanal 14 Bit, 3 GSPS-Einzel-DDC/Kanal-Breitbandempfänger mit RF-Abtastung und Rückkopplungs-IC

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Datenblatt

document-pdfAcrobat ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices datasheet (Rev. B) (Englisch) PDF | HTML

ADC32RF83

AKTIV

Datenblatt

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Produktdetails

Number of input channels

2

Resolution (Bits)

14

Sample rate (max) (Msps)

3000

Features

Decimating Filter, Ultra High Speed

Analog input BW (MHz)

3200

SFDR (dB)

66

SNR (dB)

61.1

Power consumption (typ) (mW)

6400

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of input channels

2

Resolution (Bits)

14

Sample rate (max) (Msps)

3000

Features

Decimating Filter, Ultra High Speed

Analog input BW (MHz)

3200

SFDR (dB)

66

SNR (dB)

61.1

Power consumption (typ) (mW)

6400

Operating temperature range (°C)

-40 to 85

Rating

Catalog

VQFN (RRH)

72

100 mm² 10 x 10

VQFNP (RMP)

72

100 mm² 10 x 10

14-Bit, Dual-Channel, 3-GSPS ADC
Noise Floor: –155 dBFS/Hz
RF Input Supports Up to 4.0 GHz
Aperture Jitter: 90 f_S
Channel Isolation: 95 dB at f_IN = 1.8 GHz
Spectral Performance (f_IN = 900 MHz, –2 dBFS):
- SNR: 60.1 dBFS
- SFDR: 66-dBc HD2, HD3
- SFDR: 76-dBc Worst Spur
Spectral Performance (f_IN = 1.85 GHz, –2 dBFS):
- SNR: 58.9 dBFS
- SFDR: 67-dBc HD2, HD3
- SFDR: 76-dBc Worst Spur
On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
On-Chip Input Clamp for Overvoltage Protection
Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
On-Chip Dither
On-Chip Input Termination
Input Full-Scale: 1.35 V_PP
Support for Multi-Chip Synchronization
JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel at 12.5 Gbps
Power Dissipation: 3.2 W/Ch at 3.0 GSPS
72-Pin VQFN Package (10 mm × 10 mm)

14-Bit, Dual-Channel, 3-GSPS ADC
Noise Floor: –155 dBFS/Hz
RF Input Supports Up to 4.0 GHz
Aperture Jitter: 90 f_S
Channel Isolation: 95 dB at f_IN = 1.8 GHz
Spectral Performance (f_IN = 900 MHz, –2 dBFS):
- SNR: 60.1 dBFS
- SFDR: 66-dBc HD2, HD3
- SFDR: 76-dBc Worst Spur
Spectral Performance (f_IN = 1.85 GHz, –2 dBFS):
- SNR: 58.9 dBFS
- SFDR: 67-dBc HD2, HD3
- SFDR: 76-dBc Worst Spur
On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
On-Chip Input Clamp for Overvoltage Protection
Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
On-Chip Dither
On-Chip Input Termination
Input Full-Scale: 1.35 V_PP
Support for Multi-Chip Synchronization
JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel at 12.5 Gbps
Power Dissipation: 3.2 W/Ch at 3.0 GSPS
72-Pin VQFN Package (10 mm × 10 mm)

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

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Alle anzeigen 2

	Typ	Titel		Datum
*	Data sheet	ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices datasheet (Rev. B)	PDF \| HTML	21 Dez 2021
	Application note	Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B)		05 Sep 2017

Design und Entwicklung

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RRH)	72	Ultra Librarian
VQFNP (RMP)	72	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

ADC32RF83

Zwei-Kanal 14 Bit, 3 GSPS-Einzel-DDC/Kanal-Breitbandempfänger mit RF-Abtastung und Rückkopplungs-IC

ADC32RF83

Produktdetails

Technische Dokumentation

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Support und Schulungen

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Videoreihe

Videos

Download-Möglichkeiten

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

Highspeed-ADCs (≥ 10 MSPS)

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Versionsinformationen