Gehäuseinformationen
| Gehäuse | Pins FCBGA (ALK) | 400 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 90 | JEDEC TRAY (5+1) |
Merkmale von AFE7906
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- Six RF sampling 14 bit, 3GSPS ADCs
- Maximum RF signal bandwidth:
- 4 ADCs: 1200MHz per ADC
- 6 ADCs: 600MHz per ADC
- RF frequency range: 5MHz - 12GHz
- Digital step attenuators (DSA): 25dB range, 0.5dB steps
- Single DDC (on 6 channels) or dual-band DDCs (on 4 channels)
- 16x NCOs per DDC channel
- Optional Internal PLL/VCO for ADC clocks or external clock at ADC sample rate
- Sysref alignment detector
- SerDes data interface:
- JESD204B and JESD204C compatible
- 8 SerDes transmitters up to 29.5Gbps
- Subclass 1 multi-device synchronization
- Package: 17mm × 17mm FCBGA, 0.8mm pitch
Beschreibung von AFE7906
The AFE7906 is a high performance, wide bandwidth multi-channel receiver, integrating six RF Sampling ADCs. With operation up to 12GHz, this device enables direct RF sampling in the L, S, C and X-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Four receiver channels have an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX or 600MHz.
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths (1200MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.