Produktdetails

Frequency (max) (MHz) 15000 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Wideband Current consumption (mA) 340 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 15000 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Wideband Current consumption (mA) 340 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation
  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

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* Datenblatt LMX2594 15-GHz Wideband PLLATINUM™ RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) PDF | HTML 17.04.2019
Anwendungshinweis VCO Design Basic and Key Parameter for GSM Application (Rev. A) PDF | HTML 21.04.2026
Anwendungshinweis Leveraging TI’s Clock Tools For Converter Designs PDF | HTML 20.04.2026
Anwendungshinweis Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11.04.2025
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22.10.2024
Anwendungshinweis Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03.09.2024
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 08.08.2024
Application brief Using the MSP430FR5969 EVM to Program the LMX2594 PLL Synthesizer PDF | HTML 26.04.2024
Application brief LMX2820 with Internal Doubler versus LMX2594 PDF | HTML 16.01.2024
Anwendungshinweis Streamline RF Synthesizer VCO Calibration and Optimize PLL Lock Time (Rev. A) 27.08.2021
Anwendungshinweis Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization 11.11.2020
Anwendungshinweis Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter PDF | HTML 30.09.2020
Technischer Artikel Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML 04.06.2019
Technischer Artikel Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy PDF | HTML 28.08.2017
Technischer Artikel How to implement FM modulation PDF | HTML 03.08.2017
Technischer Artikel High-speed data converter clocking for JESD204B PDF | HTML 07.07.2017

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