Gehäuseinformationen
| Gehäuse | Pins VQFNP (RTC) | 48 |
| Betriebstemperaturbereich (°C) -55 to 125 |
| Gehäusemenge | Träger 260 | JEDEC TRAY (10+1) |
Merkmale von LMX2694-SEP
- VID V62/19616 -02XE
- 39.3-MHz to 15.1-GHz output frequency
- –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
- 54-fs RMS jitter at 8 GHz (100 Hz to 100 MHz)
- Programmable output power
- PLL key specifications
- Figure of merit: –236 dBc/Hz
- Normalized 1/f noise: –129 dBc/Hz
- Up to 200-MHz phase detector frequency
- Synchronization of output phase across multiple devices
- Support for SYSREF with 9-ps resolution programmable delay
- 3.3-V single power supply operation
- Operating temperature range: –55°C to 125°C
- Radiation specifications
- Single event latch-up >43 MeV-cm2/mg
- Total ionizing dose to 30 krad(Si)
Beschreibung von LMX2694-SEP
The LMX2694-SEP device is a high-performance, wideband phase-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) and voltage regulators that can output any frequency between 39.3 MHz and 15.1 GHz without a doubler, eliminating the need for ½ harmonic filters. The VCO on this device covers an entire octave to complete the frequency coverage down to 39.3 MHz. The high-performance PLL, with a –236-dBc/Hz figure of merit and high-phase detector frequency, can achieve very low in-band noise and integrated jitter.
The LMX2694-SEP allows designers to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in any use case, including one with the fractional engine or output divider enabled. The device also allows designers to generate or repeat SYSREF (compliant to JESD204B standard) to use the device as a low-noise clock source for high-speed data converters.