Gehäuseinformationen
| Gehäuse | Pins CPGA (GFA) | 141 |
| Betriebstemperaturbereich (°C) -55 to 125 |
| Gehäusemenge | Träger 21 | JEDEC TRAY (5+1) |
Merkmale von SMJ320C50
- Military Operating Temperature Range:
- 55°C to 125°C
- Processed to MIL-PRF-38535
- Fast Instruction Cycle Time (30 ns and 40 ns)
- Source-Code Compatible With All C1x and C2x Devices
- RAM-Based Operation
- 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM
- 1056 × 16-Bit Dual-Access On-Chip Data RAM
- 2K × 16-Bit On-Chip Boot ROM
- 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
- 32-Bit Arithmetic Logic Unit (ALU)
- 32-bit Accumulator (ACC)
- 32-Bit Accumulator Buffer (ACCB)
- 16-Bit Parallel Logic Unit (PLU)
- 16 × 16-Bit Multiplier, 32-Bit Product
- 11 Context-Switch Registers
- Two Buffers for Circular Addressing
- Full-Duplex Synchronous Serial Port
- Time-Division Multiplexed Serial Port (TDM)
- Timer With Control and Counter Registers
- 16 Software Programmable Wait-State Generators
- Divide-by-One Clock Option
- IEEE 1149.1
Boundary Scan Logic - Operations Are Fully Static
- Enhanced Performance Implanted CMOS (EPIC™) Technology Fabricated by Texas Instruments
- Packaging
- 141-Pin Ceramic Grid Array (GFA Suffix)
- 132-Lead Ceramic Quad Flat Package (HFG Suffix)
- 132-Lead Plastic Quad Flat Package (PQ Suffix)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC is a trademark of Texas Instruments Incorporated.
Beschreibung von SMJ320C50
The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-um double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.
A number of enhancements to the basic SMJ320C2x architecture give the C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.
The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 uA. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.
The C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time, and 66 MHz, providing a 30-ns cycle time. The available options are listed in Table 1.