Produktdetails

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 9 IOL (max) (mA) 48 IOH (max) (mA) -24 Input type TTL Output type TTL Features High speed (tpd 10-50ns) Technology family BCT Rating Catalog Operating temperature range (°C) 0 to 70
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 9 IOL (max) (mA) 48 IOH (max) (mA) -24 Input type TTL Output type TTL Features High speed (tpd 10-50ns) Technology family BCT Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • BiCMOS Process With TTL Inputs and Outputs
  • State-of-the-Art BiCMOS Design Significantly Reduces Standby Current
  • Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
  • Functionally Equivalent to AMD Am29854
  • High-Speed Bus Transceiver With Parity Generator/Checker
  • Parity-Error Flag With Open-Collector Output
  • Latch for Storage of the Parity-Error Flag
  • Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
  • BiCMOS Process With TTL Inputs and Outputs
  • State-of-the-Art BiCMOS Design Significantly Reduces Standby Current
  • Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
  • Functionally Equivalent to AMD Am29854
  • High-Speed Bus Transceiver With Parity Generator/Checker
  • Parity-Error Flag With Open-Collector Output
  • Latch for Storage of the Parity-Error Flag
  • Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)

The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (, ) inputs can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag. can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.

The SN74BCT29854 is characterized for operation from 0°C to 70°C.

 

The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (, ) inputs can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag. can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.

The SN74BCT29854 is characterized for operation from 0°C to 70°C.

 

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 8-Bit To 9-Bit Parity Bus Transceiver datasheet 01 Nov 1993
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996

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