Gehäuseinformationen
| Gehäuse | Pins SOIC (D) | 14 |
| Betriebstemperaturbereich (°C) 0 to 70 |
| Gehäusemenge | Träger 2.500 | LARGE T&R |
Merkmale von SN74LS73A
- Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
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Beschreibung von SN74LS73A
The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.