Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 14 |
| Betriebstemperaturbereich (°C) -55 to 125 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von SN74LV4T125-EP
- Wide operating range of 1.8V to 5.5V
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Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
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Up translation:
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1.2V to 1.8V
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1.5V to 2.5V
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1.8V to 3.3V
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3.3V to 5.0V
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Down translation:
- 5.0V, 3.3V, 2.5V to 1.8V
- 5.0V, 3.3V to 2.5V
- 5.0V to 3.3V
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- 5.5V tolerant input pins
- Supports standard pinouts
- Up to 150Mbps with 5V or 3.3V VCC
- Latch-up performance exceeds 250mA per JESD 17
Beschreibung von SN74LV4T125-EP
The SN74LV4T125-EP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).