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SN74LVC1G02-EP

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Verbessertes Produkt, Einzel-NOR-Gatter mit 2 Eingängen, 1,65 V bis 5,5 V

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Datenblatt

SN74LVC1G02-EP

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Datenblatt Jetzt bestellen

Produktdetails

Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm)
  • Controlled Baseline
    • One Assembly
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Available in the Texas Instruments NanoStar and NanoFree Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

NanoStar Is a trademark of Texas InstrumentsNanoFree Is a trademark of Texas Instruments
  • Controlled Baseline
    • One Assembly
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Available in the Texas Instruments NanoStar and NanoFree Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

NanoStar Is a trademark of Texas InstrumentsNanoFree Is a trademark of Texas Instruments

This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G02 performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G02 performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SN74LVC1G02-EP datasheet 02.06.2006
* Strahlungs- und Zuverlässigkeitsbericht SN74LVC1G02MDCKREP Reliability Report 26.08.2011
* VID SN74LVC1G02-EP VID V6206631 21.06.2016

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