Gehäuseinformationen
| Gehäuse | Pins SSOP (DCT) | 8 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von SN74LVC2G74
- Available in the Texas Instruments NanoFree™ package
- Supports 5 V VCC operation
- Inputs accept voltages to 5.5 V
- Maximum tpd of 5.9 ns at 3.3 V
- Low power consumption, 10 µA maximum ICC
- ±24 mA output drive at 3.3 V
- Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
- Ioff supports live insertion, partial-power-down mode, and back-drive protection
- Latch-up performance exceeds 100 mA Per JESD 78, class II
- ESD protection exceeds JESD 22
- 2000 V human-body model
- 200 V machine model
- 1000 V charged-device model
Beschreibung von SN74LVC2G74
This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.