SN74LVCH16244A

AKTIV

Produktdetails

Technology family LVC Number of channels 16 IOL (max) (mA) 24 Supply current (max) (µA) 20 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 16 IOL (max) (mA) 24 Supply current (max) (µA) 20 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm) TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm)
  • Member of the Texas Instruments
    Widebus Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input or Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Member of the Texas Instruments
    Widebus Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input or Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The SN74LVCH16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The SN74LVCH16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SN74LVCH16244A 16-Bit Buffer/Driver With 3-State Outputs datasheet (Rev. B) PDF | HTML 07.11.2013
Anwendungshinweis An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17.09.2018
Anwendungshinweis Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 23.02.2005

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationsmodell

SN74LVCH16244A Behavioral SPICE Model

SCAM093.ZIP (7 KB) - PSpice-Modell
Unterstützte Produkte und Hardware
Simulationsmodell

SN74LVCH16244A IBIS Model (Rev. B)

SCEM069A (10 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian

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