TMS320C6414

Name: TMS320C6414
Brand: TI
SKU: TMS320C6414
Price: 85.55 USD

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C64x Festkomma-DSP – bis zu 720MHz, McBSP

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Datenblatt

document-pdfAcrobat TMS320C6414, TMS320C6415, TMS320C6416 Fixed-Point Digital Signal Processors datasheet (Rev. N) (Englisch)

Fehlerverzeichnis

document-pdfAcrobat
TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) (Rev. T) (Englisch)

TMS320C6414

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Datenblatt

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Produktdetails

DSP type

1 C64x

DSP (max) (MHz)

500, 600, 720

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

DSP type

1 C64x

DSP (max) (MHz)

500, 600, 720

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

FCBGA (GLZ)

532

529 mm² 23 x 23

FCBGA (ZLZ)

532

529 mm² 23 x 23

Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C62x™
- C6414/15/16 Devices Pin-Compatible
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
- Supports Over 600 7.95-Kbps AMR
- Programmable Code Parameters
Turbo Decoder Coprocessor (TCP) [C6416]
- Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)
- One 64-Bit (EMIFA), One 16-Bit (EMIFB)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1280M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Host-Port Interface (HPI)
- User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
- Three PCI Bus Address Registers:
  Prefetchable Memory
  Non-Prefetchable Memory I/O
- Four-Wire Serial EEPROM Interface
- PCI Interrupt Request Under DSP Program Control
- DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
- Direct Interface to T1/E1, MVIP, SCSA Framers
- Up to 256 Channels Each
- ST-Bus-Switching-, AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414, TMS320C6415, and TMS320C6416 shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416.
These C64xdevices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C62x™
- C6414/15/16 Devices Pin-Compatible
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
- Supports Over 600 7.95-Kbps AMR
- Programmable Code Parameters
Turbo Decoder Coprocessor (TCP) [C6416]
- Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)
- One 64-Bit (EMIFA), One 16-Bit (EMIFB)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1280M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Host-Port Interface (HPI)
- User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
- Three PCI Bus Address Registers:
  Prefetchable Memory
  Non-Prefetchable Memory I/O
- Four-Wire Serial EEPROM Interface
- PCI Interrupt Request Under DSP Program Control
- DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
- Direct Interface to T1/E1, MVIP, SCSA Framers
- Up to 256 Channels Each
- ST-Bus-Switching-, AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)

The TMS320C64x™ DSPs (including the TMS320C6414, TMS320C6415, and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™ developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 600 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to forty-three 384-Kbps or seven 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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	Typ	Titel		Datum
*	Data sheet	TMS320C6414, TMS320C6415, TMS320C6416 Fixed-Point Digital Signal Processors datasheet (Rev. N)		26 Mai 2005
*	Errata	TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) (Rev. T)		01 Aug 2007
	Application note	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	19 Mai 2021
	User guide	Emulation and Trace Headers Technical Reference Manual (Rev. I)		09 Aug 2012
	Application note	Introduction to TMS320C6000 DSP Optimization		06 Okt 2011
	User guide	TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J)		30 Jul 2010
	User guide	TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)		02 Jul 2009
	Application note	Migrating from TMS320C6416/15/14 to TMS320C6416T/15T/14T (Rev. B)		22 Feb 2008
	Application note	TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)		04 Sep 2007
	User guide	TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)		11 Apr 2007
	Product overview	TMS320C6000 DSP TCP/IP Stack Software (Rev. C)		04 Apr 2007
	User guide	TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)		14 Dez 2006
	User guide	TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C)		15 Nov 2006
	User guide	TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C)		28 Feb 2006
	User guide	TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C)		01 Jan 2006
	Application note	TMS320C6414 Hardware Designer's Resource Guide (Rev. A)		22 Okt 2005
	Application note	Migrating from TMS320C64x to TMS320C64x+ (Rev. A)		20 Okt 2005
	Application note	TMS320C6000 EMIF to USB Interfacing Using Cypress EZ-USB SX2 (Rev. A)		20 Mai 2005
	User guide	TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)		01 Mär 2005
	User guide	TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)		25 Jan 2005
	Application note	Migrating From TMS320C6416/15/14/11 Rev 1.1 to Rev 2.0		19 Okt 2004
	Application note	Use and Handling of Semiconductor Packages With ENIG Pad Finishes		31 Aug 2004
	User guide	TMS320C6000 Chip Support Library API Reference Guide (Rev. J)		13 Aug 2004
	Application note	TMS320C64x Reference Design		12 Mai 2004
	Application note	TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)		26 Apr 2004
	Application note	TMS320C6000 Board Design: Considerations for Debug (Rev. C)		21 Apr 2004
	User guide	TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A)		25 Mär 2004
	Application note	TMS320C6000 McBSP Initialization (Rev. C)		08 Mär 2004
	Application note	TMS320C6000 EDMA IO Scheduling and Performance		05 Mär 2004
	Application note	TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance		31 Okt 2003
	Application note	TMS320C64x DSP Host Port Interface (HPI) Performance		24 Okt 2003
	Application note	Tips for Using the EDMA with the Utopia Port		15 Sep 2003
	User guide	TMS320C6000 DSP Designing for JTAG Emulation Reference Guide		31 Jul 2003
	Application note	TMS320C6414/5/6 Power Consumption Summary (Rev. C)		30 Jun 2003
	User guide	TMS320C6000 DSP Cache User's Guide (Rev. A)		05 Mai 2003
	Application note	Using IBIS Models for Timing Analysis (Rev. A)		15 Apr 2003
	Application note	How to Begin Development Today With the TMS320C6414, C6415, and C6416 DSPs (Rev. A)		06 Mär 2003
	Application note	TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)		04 Jun 2002
	Application note	TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)		17 Apr 2002
	Application note	TMS320C6000 Board Design for JTAG (Rev. C)		02 Apr 2002
	Application note	TMS320C6000 EMIF to External Flash Memory (Rev. A)		13 Feb 2002
	Application note	Cache Usage in High-Performance DSP Applications with the TMS320C64x		13 Dez 2001
	Application note	Using a TMS320C6000 McBSP for Data Packing (Rev. A)		31 Okt 2001
	Application note	TMS320C6000 Enhanced DMA: Example Applications (Rev. A)		24 Okt 2001
	Application note	Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)		30 Sep 2001
	Application note	TMS320C6000 Host Port to MC68360 Interface (Rev. A)		30 Sep 2001
	Application note	TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)		31 Aug 2001
	Application note	TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)		31 Aug 2001
	Application note	Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)		31 Aug 2001
	Application note	TMS320C6000 System Clock Circuit Example (Rev. A)		15 Aug 2001
	Application note	TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)		23 Jul 2001
	Application note	TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)		10 Jul 2001
	Application note	TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)		30 Jun 2001
	Application note	TMS320C6000 Host Port to MPC860 Interface (Rev. A)		21 Jun 2001
	Application note	TMS320C6000 McBSP: IOM-2 Interface (Rev. A)		21 Mai 2001
	Application note	TMS320C6415/6416: Using PCI EEPROM Interface and McBSP2 in a Single System		01 Mär 2001
	User guide	TMS320C64x Technical Overview (Rev. B)		30 Jan 2001
	Application note	Circular Buffering on TMS320C6000 (Rev. A)		12 Sep 2000
	Application note	TMS320C6000 McBSP as a TDM Highway (Rev. A)		11 Sep 2000
	Application note	TMS320C6000 u-Law and a-Law Companding with Software or the McBSP		02 Feb 2000
	Application note	General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point		31 Jan 2000
	Application note	TMS320C6000 C Compiler: C Implementation of Intrinsics		07 Dez 1999
	Application note	TMS320C6000 McBSP: I2S Interface		08 Sep 1999

Design und Entwicklung

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Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7). Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Anwendungssoftware und Frameworks

SPRC137 — TMS320C6414/C6415/C6416 Referenzdesign

TI provides a reference design with commonly used configurations that allow customers to get maximum performance effortlessly from TMS320C64x™ DSP based systems. For extreme high performance, an SDRAM only interface is designed to run at speeds up to 150 MHz. The reference design also includes a (...)

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AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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TMS320C5517 — Energieeffizienter C55x Festkomma-DSP – bis zu 200MHz, USB, LCD-Schnittstelle, FFT HWA, SAR ADC

TMS320C5532 — C55x Festkomma-DSP mit geringem Stromverbrauch – bis zu 100 MHz

TMS320C5533 — C55x Festkomma-DSP mit geringem Stromverbrauch – bis zu 100 MHz, USB

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TMS320C6701 — C67x Fließkomma-DSP – bis zu 167MHz, McBSP

TMS320C6711D — C67x-Fließkomma-DSP – bis zu 250 MHz, McBSP, 32-Bit-EMIFA

TMS320C6712D — C67x Fließkomma-DSP – bis zu 150MHz, McBSP, 16-Bit EMIFA

TMS320C6720 — C67x Fließkomma-DSP – 200 MHz, McASP, 16-Bit-EMIFA

TMS320C6722B — C67x Fließkomma-DSP – bis zu 250 MHz, McASP, 16-Bit-EMIFA

TMS320C6726B — C67x Fließkomma-DSP – bis zu 266 MHz, McASP, 16-Bit-EMIFA

TMS320C6727 — C67x Fließkomma-DSP – bis zu 250MHz, McASP, 32-Bit-EMIFA

TMS320C6727B — C67x Fließkomma-DSP – bis zu 350 MHz, McASP, 32-Bit-EMIFA

TMS320C6743 — Energieeffizienter C674x-Fließkomma-DSP – 375 MHz

TMS320C6745 — C674x Fließkomma-DSP mit geringem Stromverbrauch – 456MHz, QFP

TMS320C6747 — C674x Fließkomma-DSP mit geringem Stromverbrauch – 456 MHz, PBGA

TMS320DM642Q — Digitaler Festkomma-Signalprozessor für Video/Bildverarbeitung

TMS320DM6431Q — Digitaler Medienprozessor, bis zu 2400 MIPS, 300-MHz-Taktrate

TMS320DM6435Q — Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 1 McBSP

TMS320DM6437Q — Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 2 McBSP

TMS320DM6441 — DaVinci Digital-Media-System-on-Chip

TMS320DM6467T — System-on-Chip für digitale Medien

TMS320DM647 — Digital-Media-Prozessor

Download-Optionen

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FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors