Gehäuseinformationen
| Gehäuse | Pins HTSSOP (DDV) | 44 |
| Betriebstemperaturbereich (°C) 0 to 70 |
| Gehäusemenge | Träger 2.000 | LARGE T&R |
Merkmale von TPA3255
- Differential Analog Inputs
- Total Output Power at 10%THD+N
- 315-W Stereo into 4 Ω in BTL Configuration
- 185-W Stereo into 8 Ω in BTL Configuration
- 600-W Mono into 2 Ω in PBTL Configuration
- Total Output Power at 1%THD+N
- 260-W Stereo into 4 Ω in BTL Configuration
- 150-W Stereo into 8 Ω in BTL Configuration
- 480-W Mono into 2 Ω in PBTL Configuration
- Advanced Integrated Feedback Design with High-speed
Gate Driver Error Correction
(PurePath™ Ultra-HD)- Signal Bandwidth up to 100 kHz for High Frequency Content From HD Sources
- Ultra Low 0.006% THD+N at 1 W into 4 Ω and <0.01% THD+N to Clipping
- >65 dB PSRR (BTL, 1 kHz, No Input Signal)
- <85 µV (A-Weighted) Output Noise
- >111 dB (A Weighted) SNR
- Multiple Configurations Possible:
- Stereo, Mono, 2.1 and 4xSE
- Click and Pop Free Startup and Stop
- 90% Efficient Class-D Operation (4 Ω)
- Wide 18-V to 53.5V Supply Voltage Operation
- Self-Protection Design (Including Undervoltage, Overtemperature, Clipping, and Short Circuit Protection) With Error Reporting
- EMI Compliant When Used With Recommended System Design
Beschreibung von TPA3255
TPA3255 is a high performance class-D power amplifier that enables true premium sound quality with class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. The device is operated in AD-mode, and can drive up to 2 x 315 W into 4-Ω load at 10% THD and 2 x 150 W unclipped into 8-Ω load and features a 2 VRMS analog input interface that works seamlessly with high performance DACs such as TI’s PCM5242. In addition to excellent audio performance, TPA3255 achieves both high power efficiency and very low power stage idle losses below 2.5W. This is achieved through the use of 85 mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.