Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADC12D1600QML-SP

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Radiation-hardened, 300krad, 12-bit dual 1.6GSPS or single 3.2GSPS ADC

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ADC12D1600QML-SP

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Detalles del producto

Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 58.2 ENOB (Bits) 9.3 SFDR (dB) 67.3 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 58.2 ENOB (Bits) 9.3 SFDR (dB) 67.3 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA (NAA) 376 780.6436 mm² (0 mm × 0 mm)
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos ADC12D1600QML 12-Bit, 3.2/2.0 GSPS RF Sampling ADC datasheet 17/12/2012
* Informe de radiación y confiabilidad ADC12D1600QML-SP/ADC12D1620QML-SP Single-Event Effects (SEE) Radiation Report 27/07/2020
* Informe de radiación y confiabilidad Single Event Effects Characterization of Texas Instruments ADC12D1600CCMLS 14/06/2018
* Informe de radiación y confiabilidad ADC12D1600CCMLS TID Report 17/01/2013
* Informe de radiación y confiabilidad Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 4/05/2012
Guía de selección TI Space Products (Rev. L) 27/03/2026
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 17/06/2025
Nota sobre la aplicación Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 10/06/2025
Más documentación TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 20/02/2025
Nota sobre la aplicación Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19/10/2022
Application brief Understanding Op Amp Noise in Audio Circuits PDF | HTML 14/06/2021
Nota sobre la aplicación AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 3/02/2017
Nota sobre la aplicación Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCs 7/12/2015
Nota sobre la aplicación Signal Chain Noise Figure Analysis 29/10/2014
Nota sobre la aplicación Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 6/08/2014
Nota sobre la aplicación AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 1/05/2013
Nota sobre la aplicación From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18/12/2012
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 16/05/2012

Diseño y desarrollo

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Modelo de simulación

ADC12D1600 IBIS Model (Rev. A)

SNAM125A.ZIP (43 KB) - Modelo IBIS
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
CCGA (NAA) 376 Ultra Librarian
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