The ADC31RF80 device is a 14-bit, 3-GSPS, single-channel telecom receiver and feedback device that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC31RF80 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
The ADC31RF80 comes with a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC31RF80 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
| Documentación principal | Tipo | Título | Opciones de formato | Fecha |
|---|---|---|---|---|
| * | Data sheet | ADC31RF80 3-GSPS Telecom Receiver and Feedback Device datasheet | PDF | HTML | 23 ago 2017 |
| Application note | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | 05 sep 2017 |
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El módulo de evaluación (EVM) ADC32RF80 demuestra el rendimiento de un convertidor analógico a digital (ADC) doble de 3 GSPS y 14 bits con la interfaz JESD204B. El EVM incluye el dispositivo ADC32RF80, y la sincronización JESD204B la proporcionan el LMK04828 y los reguladores de tensión de TI para (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
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