Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)
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ADC32RF72

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ADC32RF72

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Detalles del producto

Sample rate (max) (Msps) 1500 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 1800 Features Bypass Mode, Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Internal Reference Rating Catalog Peak-to-peak input voltage range (V) 1.4 Power consumption (typ) (mW) 3100 SNR (dB) 72.1 ENOB (Bits) 11.8 SFDR (dB) 68 Operating temperature range (°C) -40 to 105 Input buffer Yes
Sample rate (max) (Msps) 1500 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 1800 Features Bypass Mode, Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Internal Reference Rating Catalog Peak-to-peak input voltage range (V) 1.4 Power consumption (typ) (mW) 3100 SNR (dB) 72.1 ENOB (Bits) 11.8 SFDR (dB) 68 Operating temperature range (°C) -40 to 105 Input buffer Yes
FCCSP (ANH) 289 190.44 mm² (13.8 mm × 13.8 mm)
  • 16-bit, dual channel 1.5GSPS ADC
  • Noise spectral density: -163.7dBFS/Hz
  • Thermal Noise: 75.6dBFS
  • Noise figure: 14.4dB
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 40fs
  • Buffered analog inputs
  • Input fullscale: 1.44Vpp (4.1dBm)
  • Full power input bandwidth (-3dB): 1.8GHz
  • Ultra-low close-in residual phase noise:
    • −140dBc/Hz at 10kHz offset at 1GHz
  • Spectral performance (fIN = 1GHz, -1dBFS):
    • SNRflat: 72.1dBFS
    • HD2,3: 68dBc
    • Non HD2,3: 93dBFS
  • 192-tap/ch programmable FIR equalizer filter
  • 12-bit Fractional delay filter
  • Digital down-converters (DDCs)
    • Up to 8 DDC
    • Complex output: /2, /3, /4, /5 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1µs
  • JESD204B/C serial data interface
    • Maximum lane rate: 24.75Gbps
  • Code error rate (CER): 1E-15 errors/sample
  • Power consumption: 1.5W/channel (1.5GSPS)
  • 16-bit, dual channel 1.5GSPS ADC
  • Noise spectral density: -163.7dBFS/Hz
  • Thermal Noise: 75.6dBFS
  • Noise figure: 14.4dB
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 40fs
  • Buffered analog inputs
  • Input fullscale: 1.44Vpp (4.1dBm)
  • Full power input bandwidth (-3dB): 1.8GHz
  • Ultra-low close-in residual phase noise:
    • −140dBc/Hz at 10kHz offset at 1GHz
  • Spectral performance (fIN = 1GHz, -1dBFS):
    • SNRflat: 72.1dBFS
    • HD2,3: 68dBc
    • Non HD2,3: 93dBFS
  • 192-tap/ch programmable FIR equalizer filter
  • 12-bit Fractional delay filter
  • Digital down-converters (DDCs)
    • Up to 8 DDC
    • Complex output: /2, /3, /4, /5 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1µs
  • JESD204B/C serial data interface
    • Maximum lane rate: 24.75Gbps
  • Code error rate (CER): 1E-15 errors/sample
  • Power consumption: 1.5W/channel (1.5GSPS)

The ADC32RF72 is a 16-bit, 1.5GSPS (non-interleaved), dual channel analog to digital converter (ADC). The device is designed for the highest signal-to-noise ratio (SNR) and delivers a noise spectral density of −163.7dBFS/Hz. Using internal averaging modes, the NSD can be improved to as low as -166.2dBFS/Hz. The buffered analog inputs support a programmable internal termination impedance of 50, 100, 200Ω with a full power input bandwidth of 1.8GHz (−3dB). The device lets the user select one input from IN1/2/3 in addition to IN0.

The device includes several digital processing features such as a 192-tap/ch programmable FIR filter for equalization, a 12-bit fractional delay filter as well as multiple digital down converters (DDCs). There are eight DDCs supporting decimation factors of /2, /3 and /5 up to /32768. The 48-bit NCOs support phase coherent frequency hopping.

The ADC32RF72 supports the JESD204B/C serial data interface with interface rates up to 24.75Gbps. The power efficient ADC architecture consumes 1.5W/ch at 1.5GSPS and provides power scaling with lower sampling rates.

The ADC32RF72 is a 16-bit, 1.5GSPS (non-interleaved), dual channel analog to digital converter (ADC). The device is designed for the highest signal-to-noise ratio (SNR) and delivers a noise spectral density of −163.7dBFS/Hz. Using internal averaging modes, the NSD can be improved to as low as -166.2dBFS/Hz. The buffered analog inputs support a programmable internal termination impedance of 50, 100, 200Ω with a full power input bandwidth of 1.8GHz (−3dB). The device lets the user select one input from IN1/2/3 in addition to IN0.

The device includes several digital processing features such as a 192-tap/ch programmable FIR filter for equalization, a 12-bit fractional delay filter as well as multiple digital down converters (DDCs). There are eight DDCs supporting decimation factors of /2, /3 and /5 up to /32768. The 48-bit NCOs support phase coherent frequency hopping.

The ADC32RF72 supports the JESD204B/C serial data interface with interface rates up to 24.75Gbps. The power efficient ADC architecture consumes 1.5W/ch at 1.5GSPS and provides power scaling with lower sampling rates.
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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos ADC32RF72 Dual Channel 1.5GSPS 16-bit RF Sampling ADC datasheet PDF | HTML 20/11/2025
Analog Design Journal Sampling around Nyquist holes in high-speed converters PDF | HTML 16/05/2025
Nota sobre la aplicación Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 28/03/2025
Nota sobre la aplicación Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 26/03/2025

Diseño y desarrollo

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Software de aplicación y estructura

ADC3XRF7X-API-APPSW — Software development package for ADC3XRF7X device family

ADC3XRF7X software development kit
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