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Microcontroladores (MCU) y procesadores
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SoC de redes industriales y multimedia

AM6528

ACTIVO

Procesador Sitara: Arm Cortex-A53 doble y Arm Cortex-R5F doble, Gigabit PRU-ICSS, gráficos 3D

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AM6528

ACTIVO
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Detalles del producto

CPU 2 Arm Cortex-A53 Frequency (MHz) 1100 Coprocessors 2 Arm Cortex-R5F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols EtherCAT, Ethernet, ICSS, Profibus, Profinet, TSN PCIe 2 PCIe Gen 3 Hardware accelerators CPU only Features Networking Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
CPU 2 Arm Cortex-A53 Frequency (MHz) 1100 Coprocessors 2 Arm Cortex-R5F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols EtherCAT, Ethernet, ICSS, Profibus, Profinet, TSN PCIe 2 PCIe Gen 3 Hardware accelerators CPU only Features Networking Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
FCCSP (ACD) 784 529 mm² (23 mm × 23 mm)

Processor cores:

  • Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm Cortex-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core

    Industrial subsystem:

  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG

    Memory subsystem:

  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR4 memory types up to DDR-1600
    • 32-bit data bus and 7-bit SECDED bus
    • 8 GB of total addressable space
  • General-Purpose Memory Controller (GPMC)

    Functional Safety:

  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware Integrity up to SIL 2
    • Safety-related certification
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm Cortex-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC

    Security:

  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security software

    SoC services:

  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)

    Multimedia:

  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI DPI parallel interface
    • One port OLDI
  • PowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)

    High-speed interfaces:

  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express ( PCIe) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    General connectivity:

  • 6× Inter-Integrated Circuit ( I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins

    Control interfaces:

  • 6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules

    Automotive interfaces:

  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (MCASP) modules

    Media and data storage:

  • 2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfaces

    Simplified power management:

  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients

    Analog/system integration:

  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change

    System-on-Chip (SoC) architecture:

  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

Processor cores:

  • Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm Cortex-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core

    Industrial subsystem:

  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG

    Memory subsystem:

  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR4 memory types up to DDR-1600
    • 32-bit data bus and 7-bit SECDED bus
    • 8 GB of total addressable space
  • General-Purpose Memory Controller (GPMC)

    Functional Safety:

  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware Integrity up to SIL 2
    • Safety-related certification
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm Cortex-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC

    Security:

  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security software

    SoC services:

  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)

    Multimedia:

  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI DPI parallel interface
    • One port OLDI
  • PowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)

    High-speed interfaces:

  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express ( PCIe) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    General connectivity:

  • 6× Inter-Integrated Circuit ( I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins

    Control interfaces:

  • 6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules

    Automotive interfaces:

  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (MCASP) modules

    Media and data storage:

  • 2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfaces

    Simplified power management:

  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients

    Analog/system integration:

  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change

    System-on-Chip (SoC) architecture:

  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.

AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos AM654x, AM652x Sitara™ Processors Silicon Revision 2.1 datasheet (Rev. C) PDF | HTML 15/09/2023
* Guía del usuario AM65x/DRA80xM Processors Technical Reference Manual (Rev. E) 18/12/2019
* Errata AM65x Processors Silicon Revision 2.1/2.0/1.0 (Rev. I) PDF | HTML 4/05/2023
Nota sobre la aplicación Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 17/10/2025
Guía del usuario TPS65941319-Q1 PMIC User Guide for Sitara AM65 Processors (Rev. A) PDF | HTML 25/06/2025
Informe Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26/02/2025
Nota sobre la aplicación MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14/05/2024
Nota sobre la aplicación Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15/11/2023
Informe Time Sensitive Networking for Industrial Automation (Rev. C) PDF | HTML 31/07/2023
Nota sobre la aplicación Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24/05/2023
Nota sobre la aplicación High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24/02/2023
Nota sobre la aplicación Hardware Design Guide for AM65x Devices (Rev. A) PDF | HTML 22/12/2022
Nota sobre la aplicación PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 11/10/2022
Nota sobre la aplicación AM65x/DRA80x Schematic Checklist (Rev. A) PDF | HTML 26/07/2021
Informe EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 28/07/2020
Nota sobre la aplicación AM65x/DRA80xM EMIF Tools (Rev. B) 4/03/2020
Libro electrónico E-book: An engineer’s guide to industrial robot designs 12/02/2020
Nota sobre la aplicación AM65xx Time Synchronization Architecture PDF | HTML 14/10/2019
Nota sobre la aplicación Enabling Android Automotive on Your TI Development Board PDF | HTML 12/07/2019
Nota sobre la aplicación AM65x DDR ECC Initialization and Testing 8/03/2019
Nota sobre la aplicación AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A) 7/03/2019
Informe Virtualization for embedded industrial systems (Rev. B) 7/03/2019
Nota sobre la aplicación Integrating a WiLink8 Module with the AM65x EVM 29/01/2019
Nota sobre la aplicación PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 18/01/2019
Nota sobre la aplicación PRU Read Latencies (Rev. A) 21/12/2018
Nota sobre la aplicación PRU-ICSS Getting Starting Guide on Linux (Rev. A) PDF | HTML 10/12/2018
Informe Ensuring real-time predictability (Rev. B) 4/12/2018
Nota sobre la aplicación AM65xx System Performance 30/11/2018
Informe The state of functional safety in Industry 4.0 27/11/2018
Nota sobre la aplicación PRU-ICSS / PRU_ICSSG Migration Guide PDF | HTML 5/11/2018
Informe Secure Boot on embedded Sitara™ processors (Rev. A) 13/10/2018
Informe Designing industrial controls for Industry 4.0 with Sitara™ AM6x processors 11/10/2018
Guía del usuario AM654x/DRA80xM BGA Escape Routing Stackup PDF | HTML 29/08/2018
Informe Designing Embedded Systems for High Reliability With Sitara AM6x Processors PDF | HTML 28/08/2018

Diseño y desarrollo

Soluciones de alimentación

Busque las soluciones de alimentación disponibles para el AM6528. TI ofrece soluciones de alimentación para sistemas en chip (SoC), procesadores, microcontroladores, sensores y matrices de compuertas programables de campo (FPGA), sean o no de TI.

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TMDSLCD1EVM — Kit de accesorios para pantalla LCD de 1280 × 800

El kit accesorio de pantalla LCD de 1280x800 es un accesorio adicional para el AM65x IDK (TMDX654IDKEVM) que permite agregar funciones táctiles y de visualización para la evaluación de HMI, PC industriales y otros casos de uso que requieran visualización. El kit de accesorios para pantalla LCD de (...)

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TMDX654IDKEVM — Kit de desarrollo industrial (IDK) AM65x

El kit de desarrollo industrial (IDK) AM65x es una plataforma de desarrollo para evaluar las capacidades de comunicación y control industrial de los procesadores Sitara™ AM65x para aplicaciones en automatización de fábricas, accionamientos, robótica, infraestructura de red y más. Los procesadores (...)

Guía del usuario: PDF | HTML
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MISTR-3P-SOM-AM65X — Sistema en Módulo (SOM) Mistral Solutions AM65x

The AM65x SOM from Mistral is an easy to use, compact, light-weight system on module (SOM) providing very high processing power for industrial applications. This module is based on Texas Instruments Sitara™ AM6548 SoC and is ideal for complex processing, connectivity and control required for (...)

Desde: Mistral Solutions Pvt. Ltd
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TQ-3P-SITARASOMS — Sistema de TQ Group en módulos para procesadores y microcontroladores basados en TI Arm

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
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Productos y hardware compatibles
Placa de evaluación

TQ-3P-SOM-TQMA65XX — Sistema TQ-Group TQMa65xx en módulo para procesador AM6528 basado en Arm

El módulo integrado TQMa65xx, basado en la tecnología ARM® Cortex®-A53 de Texas Instruments. El controlador gráfico integrado admite aplicaciones con pantalla y táctiles. Hay cuatro variantes de procesador disponibles para diversas aplicaciones, como redes, automatización industrial y sistemas de (...)

Desde: TQ-Group
Productos y hardware compatibles
Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Productos y hardware compatibles
En inventario
Límite:
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No disponible
Kit de desarrollo de software (SDK)

MCU-PLUS-SDK-AM65X — MCU+ SDK for AM65x – RTOS

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones. Todas las versiones del SDK del procesador son coherentes con (...)

Productos y hardware compatibles
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-AM65X — Linux processor SDK for AM65x

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones. Todas las versiones del SDK del procesador son coherentes con (...)

Productos y hardware compatibles
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-RT-AM65X — Linux-RT processor SDK for AM65x

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones. Todas las versiones del SDK del procesador son coherentes con (...)

Productos y hardware compatibles
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-AM65X — SDK de procesador RTOS para AM65x (no hay soporte de diseño de TI disponible. Consulte Descripción general: Aspectos destacados de RTOS para obtener más información)

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones. Todas las versiones del SDK del procesador son coherentes con (...)

Productos y hardware compatibles
IDE, configuración, compilador o depurador

C2000_CLA_SAFETI_CQKIT_RV — C2000™ and CLA safety compiler qualification kit (leverages compiler release validations)

El Kit de cualificación de compilador de seguridad se desarrolló para ayudar a los clientes a calificar el uso del compilador C/C++ ARM, C6000, C7000 o C2000/CLA de TI respecto de normas de seguridad funcional como IEC 61508 e ISO 26262.

El Kit de cualificación de compilador de seguridad:

  • Es (...)
Productos y hardware compatibles
IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

Productos y hardware compatibles
IDE, configuración, compilador o depurador

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

Productos y hardware compatibles
Sistema operativo (SO)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Productos y hardware compatibles
Sistema operativo (SO)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)

Desde: Green Hills Software
Productos y hardware compatibles
Controlador o biblioteca

WIND-3P-VXWORKS-LINUX-OS — Procesadores Wind River VxWorks y sistemas operativos de Linux

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)

Desde: Wind River Systems
Productos y hardware compatibles
Herramienta de programación de software

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash forma parte del amplio ecosistema de desarrollo CCStudio™ de TI y es una herramienta de software diseñada para programar la memoria flash integrada en los microcontroladores y dispositivos de conectividad inalámbrica de TI, así como la memoria flash integrada en los procesadores de TI. (...)

Productos y hardware compatibles
Modelo de simulación

AM654x/DRA80xM BSDL Model

SPRM724.ZIP (12 KB) - Modelo BSDL
Productos y hardware compatibles
Modelo de simulación

AM654x/DRA80xM IBIS File

SPRM737.ZIP (19753 KB) - Modelo IBIS
Productos y hardware compatibles
Modelo de simulación

AM654x/DRA80xM Thermal Models

SPRM718.ZIP (2 KB) - Modelo térmico
Productos y hardware compatibles
Herramienta de cálculo

CLOCKTREETOOL — Herramienta de árbol de reloj para Sitara, automoción, análisis de visión y procesadores de señal di

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
Productos y hardware compatibles
Herramienta de cálculo

SITARA-DDR-CONFIG-TOOL — Herramienta Sitara External Memory Interface (EMIF)

La herramienta Sitara™ EMIF es una herramienta de software que proporciona una interfaz para configurar los procesadores TI para acceder a los dispositivos de memoria DDR externos. La herramienta también optimiza la configuración del bucle de retardo bloqueado (DLL) para compensar las desviaciones (...)

Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCCSP (ACD) 784 Ultra Librarian
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